Hi all,
I did some of the investigation based on comparison of FPU based algorithms on CM4 and CM7 cores. All the code/data were placed into the single cycle memory with full utilization of modified / true Harvard architecture, it means:
- on CM4 - code in SRAM accesible via CODE bus, data in SRAM accesible via SYSTEM bus with fully utilized modified Harvard architecture
- on CM7 - code in I-TCM memory, data in DTCM memory
Most of the code (instructions) are floating point (99%), it means thay are not interleaved with integer instructions (well this is most probably caused by compiler - to be honest I have check the assembly for both codes CM4 / CM7 and they looked the same). The code mostly contains general math calculations mul, mac, sqrt, div + load / store, all in floating point. The result I am getting are confusing me. Cortex M4 shows even better results that Cortex M7.
Questions:
- are the differencies caused by cores pipelines? not sure how "dynamic branch prediction" works, if it is really posible to get branch in single cycle or it is required to flush whole pipeline (6 cycles) in a case of floating point pipeline on CM7
- what are the best practices in coding to get the best from CM7 over CM4 in floating point meaning? (not sure if the compilers are now in best condition regarding to CM7)
thanks in advance.
regards
Rastislav
Hello Rastislav,
can you provide your benchmark code?
The C code would be preferable.
Unless there is code, Ian could not give any comment, I think.
Best regards,
Yasuhiko Koumoto.
Hi Yasuhiko san,
I could not provide the benchmark code as it is customer code. However, for simplicity I did something similar (but more simple) on cosine function (9th order polynomial approximation) which is attached. I have used ICCARM compiler (IAR 7.40). The assembler code for both cases are completely the same as you can find in attachment. The number of cycles differs by 3 (CM4 in 42 cycles, CM7 in 45 cycles).
Regards