Hello experts,
recently ARM updated the Cortex-M7 information.
I think the biggest topic would be that the pipeline details were opened.
The new information says that the integer pipeline is 4 stage and the floating point pipeline is 5 stage.
However, the past information said that it was 6 stage.
From where this differences came?
I would like to know the concrete explanation for each stage.
What is the first stage, what is the second stage, what is the third stage, what is the fourth stage, and so on?
Best regards,
Yasuhiko Koumoto.
Found where it said that
https://semiaccurate.com/2015/04/30/arm-goes-great-detail-m7-core/
However
Supercharging the Embedded Device: ARM Cortex-M7
which is a lot more reliable source doesn't say anything like that.
I seriously wouldn't waste any time on that 1st article. It is a complete joke. I also noticed that numerous online references use the term "out-of-order completion" synonymously with "out-of-order execution" or "out-of-order issue". Anyway, the Cortex-M7 is an in-order processor so none of these techniques are relevant to it.
I am a bit disappointed though that SIMD is only supported in a single pipeline. It would be interesting to see how the Cortex-M7 compares to the Cortex-M4 in terms of SIMD performance. Anyone has done such a comparison and can share the results?