Can cleaning a cache line overwrite recent changes by other bus masters?

I am developing a driver for a DMA bus master device, part of an SoC powered by a Cortex M7 CPU. Suppose I have two memory locations, x and y, which map to the same cache line, which is normal, write-back cacheable memory, and suppose the following sequence of events:

1. Start with x = x1, y = y1, cache line invalid.
2. CPU reads y
3. DMA device sets x = x2, in memory
4. CPU sets y = y2
5. CPU cleans the cache line.

After 5. completes, from the point of view of the DMA device, x = ?

I think the DMA will see x = x1, here is my reasoning:

- When CPU reads y in 2., the cache line gets pulled in cache. It reads x = x1, y = y1, and is marked as valid.
- The DMA then updates x in memory, but the change is not reflected in the cache line.
- When the CPU sets y = y2, the cache line is marked as dirty.
- When the CPU cleans the cache line, as it is dirty it gets written back to memory.
- When it gets written back to memory, it reads x = x1, y = y2, thus overwriting the
change made by the DMA to x.

Does that sound like a good reasoning?

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