Hello
I've a question regarding the NVIC on Cortex M4 devices. Up until today I was under the impression that changing the priorities of a running interrupt isn't an issue in the ARMv7-M architecture, but the following pseudo-code snippet keeps triggering a hardfault on the STM32L431 device I'm currently working on.
void isr() { // do stuff NVIC_setPriority(IRQn, 10u); // do some more stuff NVIC_setPriority(IRQn, 0u); }
Checking the UFSR register I can see that the INVPC bit is set and that the EXC_RETURN value is 0xFFFFFFE9. Does this tell me anything beside that I'm having a FPU enabled?
The hardfault seems to be entered from all over the rest of the program and there doesn't seem to be any specific PC location where it happens. When I disable the interrupt first before changing it's priority back and forth the hardfault is gone end everything works fine.Could someone explain to me what's going on here? Maybe any ideas how I could isolate the fault further?