I trying to build the peripheral around Cortex-M0 IP core thorugh AHB-lite system. Right now I have to integrate Cortex-M0 with the DDR2 SRAM (1Gb) through AHB lite.
I searched on internet which shows interfacing only through core generator (MIG). Is there a way I can use Xilinx core generator to interface through AHB lite system.
I am using Atlys Xilinx Spartan 6.
I also have some example SoC design which interface 128Mb SRAM to Cortex-M0 though AHB lite for Nexsys 3 board . But the Board I am using has DDR2 RAM.
I still could not figure out what this does and LED is still all ZERO.
In this waveform, the reset get activated every couple of clock cycles. It seem the reset generation in your test bench has some problem.
Sent from my iPad
I did it this way. is it correct. The code you have given is giviing error as A1163E: Unknown opcode stack , expecting opcode or Macro
This should be fine as long as __Vectors is being treated as constant data/text and is being linked at the beginning of the final image, i.e. it is ending up at address zero.
I run the above code on cortex m0 and stimulated on LSIM but could not see 0x55 and 0xAA pattern. above stimulation result is actually for the hex code generated from this asm file
For simulation purpose you might want to reduce the initial loop counter value to a smaller size like 20.
I have changed count value as well to 20(14hex). But still i think it is branching to uninitialized memory location. I am also sending you the memory initialized after hex file generation. Still I could not see the pattern on data bus. checked in disassembly window putting break point after each line it is working but on on LSIM. I do not know the reason
Your image still starts with the two LDR instructions, you need to ensure that the first two values are the stack pointer and reset vector values. Try moving the two DCDs you have in to the area you have defined as CODE, i.e. just before the first LDR.
Please also reuse the example software project from the EDK. (Assume you are using MDK)
As Simon said the vector table is missing from your program image.
The example project setup with your program code (unused vectors removed, loop counter reduced to 20) in EDK should generate a hex file code.hex,
which should contains something like:
000003FC <= initial Main SP value
00000009 <= Reset handler starting address (LSB set to 1 for Thumb state)
48074906 <= Reset handler first instruction at 0x8
Thanks a lot. I got it working on board.
1) Where can I find Example project from the EDK?
2) For writing software code which should we prefer assembly or embedded C?
3) I have to write a filtering code and feature extraction for the same signal. I guess C would be more convenient.
4) I thought of interfacing a Add on adc to my board which connect to board through I2C. Which I think require a AHB to I2C controller
5) If I add UART to cortex M0. How do I verify that it is working fine.
You can find example project in the EDK you downloaded in sub directories like
The Keil MDK projects has file extension of .vproj
For write software code it is much more common to use C. The EDK is designed for students who are interested in low level details, that's why the examples are in assembly language.
The EDK provide example UART in one of the directories:
However, there is no I2C module, you have to design your own.
1) We need to process two signal which we are taking through ADC, do digital filtering and feature extraction(peak detection ). Take the result using UART to host PC.
2) We have already used cortex M3 processor in a kit LPC1768 and wrote codes for filtering and feature extraction using mbed complier.
which is working correct.
we have to do the same using cortex M0 core on a FPGA(ATLYS) board, will same code would work or we have to change it for cortex M0(don't know about compatibility)
3) LPC1768 had a ADC in it so we were taking signal through it and processing it. For FPGA implementation I thought of using this as a pmod peripheral
which work on I2C for transferring data. Now this data coming through ADC should be given to AHBLite which is connected to the processor.
Could you please suggest the feasibility and steps for doing the same ?
4) We are planning to use the on chip memory for our implementation. In general we create a .hex file for code and initializing the memory with this , now if we want to apply the same code to samples of data stored in the memory , how can we initialize the data memory with samples of data and access the same ?
Regarding (4), If you are only just doing FPGA prototype, yes, you can have initial values in the SRAM. There is no different from program memory which you have created. But if you are doing actual silicon chips, it is unlikely that you can do this.
Now, for the rest of the questions: may I ask you, is this a student project or commercial project?
If you are working in a commercial environment, I would recommend you to first take some additional training course to gain better understanding of the ARM architecture first. There are a number of ARM approved training centers, offering both hardware and software training courses.
See Training - ARM for details.
If you are a student, I think you might be better off to discuss with your lecturer and see if you can get additional support from your own lecturers or tutors. For details on ARM architecture, your university/college might be able to get support via the ARM University Program - ARM. Please understand that people like Simon, me and other contributors are just "helping out" in this forum from time to time and cannot (and impossible for us to) spend too much time supporting all support requests. As you are a beginner, I don't think it will be possible to guide you to design a AHB to I2C interface module here.
For now We are only doing FPGA prototyping. and our project is a student project under ARM university program. We are also in contact with Mr. Sadanand Gulwadi ARM University Program Manager Bangalore INDIA.
We did not took any training course but I read your book A definitive guide to cortex M0 and also M3 for understanding ARM architecture. But Implementation detail for these AMBA BUS architecture and adding peripheral around cortex M0 I did not find those details.
Actually What We needed for now is that whatever we did using LPC1768 (with cortex M3) on a breadboard. same thing we wanted to using FPGA with cortex M0 core running on it.
Good to know that you are already working with the university program. I will contract them to see if there is anything they can do to help.
My books are focus on MCU users, so it doesn't cover Cortex-M hardware (e.g. AHB anf FPGA) design topics.
Regarding sampling analog inputs, there are several options you should consider:
- if the two analogue inputs are stero audio inputs (L+R channels), maybe you should use I2S protocol instead. It is much easier than I2C. (Just some serial to parallel shift registers and a simple FSM).
- You can use ADC with parellel interface (there is a AHB GPIO module in the EDK).
- You can use GPIO to create bit banging operations to emulate I2C operations, which will then allow you to connect the system to a I2C module. But this means you need to have good understanding of the I2C protocol to do that.
It is good to see you getting in touch with ARM University Program.
We are currently offering a variety of teaching materials, however most of them are only available for educators (professors, lectures etc). You are welcome to suggest your supervisor or professor to adopt ARM-based teaching material to set up courses or labs.
To do that, they simply need to go to:
click "educator", and then "Register for ARM University Program Today"
We will also have some materials open for students shortly, you could follow the same steps but select "student" rather than "educator".
For any enquiry please contact: email@example.com
ARM University Program
I will surely inform my professor about the SoC lab and course material.
View all questions in Cortex-M / M-Profile forum