In AXI, does the rising and falling edge of the WVALID signal signify the start and end of a write burst? Can the WVALID signal go low before the write request for all the transfers in that burst are issued?
You'll find xREADY/xVALID signals on each channel, and they are used for hand shaking.
The receiver asserts xREADY when it is ready to receive a transfer. The sender asserts xVALID when there is valid "stuff" (*) on the channel. A transfer takes place when both are asserted at the same time.
A burst is made up of a number of transfers. These could be back-to-back, by which I mean both WVALID and WREADY being asserted continuously for a number of a number of cycles. Or, there could be gaps between each transfer, where either (or both) WVALID/WREADY are de-asserted.
(* I say "stuff" because what is being sent/received depends on the channel. For the W channel it's written data.)
suppose , In write case a axi master send the burst length is 256, wvalid is high for only 16 burst length - how long should the axi slave need to wait for the wvalid being send from axi master or axi master should discasd the transaction
There is no transaction "timeout" support in AXI, if the AXI4 master issued a transaction for 256 transfers, it MUST be able to complete those 256 transfers.
If the master has a bug then this will hopefully be detected during system validation simulations.
However if you do see some scenarios where a master or slave could permanently lock up, the only real option is to have some sort of "watchdog" slave in the system. This "watchdog" slave is a counter which counts for a system defined number of cycles before generating an interrupt. If that interrupt is then not cleared by a bus master before the counter again counts to the defined number of cycles (because the bus is deadlocked), the "watchdog" slave then causes a system reset.
If masters or slaves (illegally) decide to "discard" transactions, it is likely that the system function is already damaged, and will eventually fail, so reset will eventually be inevitable.