How should a AXI MASTER or SLAVE behave when a xREADY signal is never asserted?

Hi all,

I was trying to extract this information from the AXI specification but I didn't find any clear answer.

I wonder how should an AXI component behave if an input xREADY signal is never asserted.

Example 1: a master starts a write transaction by asserting AWVALID (and the other needed signals). That should be legal since the AWVALID is not allowed to depend AWREADY. And is also legal for the slave (even if not recommended) to assert AWREADY after AWVALID has been asserted. What happens now if AWREADY is never asserted?

Example 2: a master starts a write transaction by asserting AWVALID and the slave acknowledges it with AWREADY. Then the master asserts WVALID to write the data, but the slave hangs and never asserts WREADY. Should the master timeout? Is it possible to abort a transaction after it's started?

Thanks for the help

A

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