I read ACE specification and ARM processor documents for ACP explanation. I always have some questions about ACP.
As soon as you know, ACP exists in SCU for data coherency.
Q1: The document says that ACP usually connects to a DMA or cryptographic engine, so why does it connect to them?
Q2: who starts ACP port to transfer data from where to where?
Q3: How does ACP implement coherency in multi-core processor?
sorry,i don't konw.
Could you please consider open this question to public?
If someone answered, other users can know it.
What is ACP?
Most of ARM's MPCore processors include an ACP, or Accelerator Coherency Port. ACPs are just AXI slave ports. You can connect an AXI master to the port, and the transactions generated by that master will pass through the MPCore processor in order to reach the main memory system.
This is a way of taking a non-cache coherent master and making it cache coherent.
As the master's transactions pass through the processor, they are visible to the coherency logic in the processor. This means that should they access an address held in the processor's caches, it can take the necessary steps to ensure coherency. Exactly how this works is down to the specific MPCore processor.
Note: In practice, it would have to be a non-cached master. As the ACP only gives visibility of the bus transactions, not any up-stream caches.
Who initiates transactions over ACP?
The master (the thing you connected to the ACP). From its perspective not much has changed.
Thanks for your response. It helps me much.
I have another question.
As you said, the ACP master has no cache coherency. It does not mean it only access non-cachable memory space. Is it right?
The external master (e.g. DMA) does not itself have cache coherency, it gains it by being connected via the ACP.
What I meant by it being uncached, is the ACP only has visibility of the master's bus transactions. Imagine the external master had a cache. It reads an address, which causes a line fill. The line fill bus transaction goes via ACP, meaning it gets a cache coherent copy back. After this processor writes the address, changing the value. But the external master has no knowledge of this - and keeps using the copy in its caches. Hence ACP works well with uncached masters.
Thanks for your explanation. Got it.
Not sure I follow. If for example the ACP port is part of MPCore Processors and has an outbound AXI slave interface than it is for external Masters, eg. DMA, to help coherency for within that MPCore Processors, that is DMA can allocate to the L2 of that MPcore Processors.
I also understand the ACP port may/may not be included but if not the amount of CMOs is greater.
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