AXI3 data interleaving

Hi,

I was going through write data interleaving section in ARM AXI3 protocol. Found this statement:

"For a slave that supports write data interleaving, the order in which it receives the first data item of each transaction must be the same as the order in which it receives the addresses for the transactions."

Suppose there are 4 masters(M1,M2,M3,M4), 1 interconnect(INT) & 4 slaves(S1,S2,S3,S4). 

Nomenclature: If Rd transactions, it's shown as M1R100 where R = Rd transaction from Master= M1 & with ID=100.

Similarly for Wr transactions, it's being shown as M1W100.

Also, suppose length of transfer is 4 beats per transaction.

Questions:

1. For the statement in Bold, it means that M1W100 and M1W101 transactions should be sent in such a way to same slave that:

     Write Address channel: M1W100(address) -> M1W101(address)

     Write Data channel:     M1W100(write data 1st beat) -> M1W101(write data 1st beat) -> M1W101(write data 2nd beat) -> ...  is allowed and M1W101(write data 1st beat)->M1W100(write data 1st beat) -> M1W101(write data 2nd beat) -> ... is not allowed.

     Is the above understanding correct?

2. In case of read transactions, there is no such restriction:

     Read Address channel: M1R100(address) -> M1R101(address)

     Read data channel:      M1R100(read data 1st beat) -> M1R101(read data 1st beat) -> M1R101(read data 2nd beat) -> ...   OR   M1R101(read data 1st beat) -> M1R100(read data 1st beat) -> M1R101(read data 2nd beat)  both are allowed.

     Is the above understanding correct?

    

Regards

Utkarsh