I have general questions on why certain features of the AXI4 protocol are the way they are.
AXI4 allows a master to send the data beats before sending the address information.
I'm curious to know if this is advantageous, either in systems with a single pair of Master-Slave, or in larger systems with AXI interconnect.
It is not that the write data and write address are completely independent - The master has to know the address before sending the data - because the correct byte lanes on the data bus and the wstrb signal has to match the address alignment.
So if the master already knows the address, why not send it?