I am using Omap3515 (Arm Cortex A8). Enabled I-Cache, D-Cache, Branch Prediction and MMU.
I am getting a data abort, if I try to copy a frame buffer of 600KB from an external memory region to another external memory region. After the data abort, I could notice that the SDR i.e SDRAM is not accessible.
I have enabled MMU in such a way that PA=VA.
There is no issue if I copy less amount data.
And also, If I disable D-Cache then there is no abort and it works fine. But I would like to enable D-Cache for faster access.
Thanks and regards,
Gopu
Hello Gopu,
although I don't understand your situation well, generally speaking, the frame buffer area should not be cacheable.
Otherwise,you should clean the L1 data cache and L2 cache after writing to the frame buffer area.
Best regards,
Yasuhiko Koumoto.
Dear Yasuhiko Koumoto,
Let me try to explain the issue as follows:
External ram address range from 0x8000 0000 to 0x8080 0000
In this, I am using 0x8000 0000 to 0x8009 6000 for frame buffer.
Enabled "I Cache", "D Cache", and configured C and B bits as cacheable and bufferable for the complete frame buffer.
Then in I my code when I try to clear the memory with some pattern say 0xFF00 for every 16 bits, I could see using debugger that some of the memory in frame buffer doesn't have the value 0xFF00.
From this I understand as follows, please correct me if I am wrong.
1. Data 0xFF00 is present in the L1 cache, but not yet flushed to the virtual memory.
2. Due to this the frame buffer is not able to get 0xFF00.
3. In this scenario, Instead of checking from the debugger session, If I read the data from frame buffer through my code , will it reflect the actual value.
I have executed the following, to check the data in frame buffer, when there is an issue. But this doesn't help.
MCR p15, #0, R0, c7, c5, #4 ;SBZ Flush Prefetch Buffer[a].
MCR p15, #0, R0, c7, c5, #6 ;SBZ Flush Entire Branch Target Cache[b].
MCR p15, #0, R0, c7, c5, #7 ;MVA[c] Flush Branch Target Cache Entry, using MVA.
MCR p15,#0,R0,c7,c10,#4 ; Data Synchronization Barrier operation
MCR p15,#0,R0,c7,c10,#5 ; Data Memory Barrier operation
Thanks a lot for yur reply.
Regards,