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SMMU: Why do the software in EL1 can modify the TTB of S2 in stream table entry when stage 2 is enabled?

Hi,

I am Newbie at SMMU. I am confused that If hypervisor is enabled, Why do the software in EL1 can modify the TTB of S2 in stream table entry?

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  • Hi,

    The memory where the STE reside is usually controlled by the hypervisor running in EL2.

    The OS kernel running in EL1 has usually not access to those tables, and can therefore not control S2TTB.

Reply
  • Hi,

    The memory where the STE reside is usually controlled by the hypervisor running in EL2.

    The OS kernel running in EL1 has usually not access to those tables, and can therefore not control S2TTB.

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