I was trying to enable mmu code I created a translation table and using some as some region as Device region.
I was able to write in to this region but while reading I was getting following error.
I was running this code in el3 only.
Synchronous Current EL with SP_ELx R FAR_EL3 00000000 3007f800 R ESR_EL3 96000210 R CPSR 600003cd R SPSR_EL3 6000000d R ELR_EL3 00000000 000019b8
Any help/suggestion is very helpful for me.
Thanks in advance,
Thanks & Regards,
Which SoC? Maybe the HW register is Write Only? Or you are writing to a different address than you think you do.
When we disable it is working fine. When we enable MMU only we are hitting this issue.
Thanks & REgards,
Not enough info! Maybe you tell us which SoC, the code which does the access, the PTE of this region.
it is a custom soc. I am attaching the startup file and translation table may be this will help. It has ARCH64 (A53)architecture.
In this we are accessing the device region.
.equ DEVICE, (IDX0 | AF)
AP1 == 0 && AP2 == 0 => RW in PL1, no access in PL0!
Hi issue reolved
by this change
BLOCK_2MB (ADDR << 20), (PXN|XN), DEVICE
BLOCK_2MB (ADDR << 20), 0, DEVICE
Thanks for your help.
If this solved your problem, then you have a different one. Device memory should be mapped XN.
PXN, XN should only affect instruction fetch and execution. The ESR shows that it is a data abort due to external abort type, not from MMU table side.
View all questions in Cortex-A / A-Profile forum