Legal transactions for AXI FIXED mode

Hello,

I am currently using AXI with burst type of FIXED for writing into a fifo. its data bus width is 32 - bits.

1. So i wanted to know whether AWSIZE of 64-bits and greater are legal or no. If it is legal then how should the data be stored in the fifo space? Will the lower 32 bits be written first and then upper 32 overwriting the lower 32 bits? or just write the lower 32 bits and rest of the  data is discarded.

2. For AWLEN > 0, and the AWSIZE <= 2, is the data overwritten on the same space? So the last written data is seem in that space?

Thank you.

  • If your slave, whatever it is, has a data bus width of 32-bits, it wouldn't be illegal to signal a 64-bit transfer to it, but presumably you'd have a "downsizing" bridge component between the 64-bit bus and the 32-bit bus on your slave, and it would then generate suitable 32-bit transfers.

    So for a FIXED burst type, each 64-bit transfer is accessing 2 32-bit values, so when "downsized" you would probably then have a series of INCR2 transactions.

    Looking at your FIFO example, as you maybe want both of these 32-bit transfers in the INCR2 transaction to access the same 32-bit FIFO location, I guess you'd ignore AxADDR[2:0]. So a 64-bit write transfer actually writes twice to the FIFO, and a 64-bit read returns two 32-bit FIFO values merged into 1 64-bit read data.

    Or, if the 64-bit source is aware that the target slave is only 32-bits wide, perhaps it is writing with WSTRB set to 0x0F or 0xF0 so that only 32-bits of valid data is signaled, and then the "downsizing" logic simply has to route the relevant half of the 64-bit data bus to the 32-bit FIFO slave.

    The better solution though would be for the master accessing the FIFO to just use 32-bit access requests, and then there isn't any doubt as to what data is read or written.

    For your second question, it seems to be missing the point of what a FIFO is. It is a single address memory buffer which stores a number of data values. If you performs multiple writes to the FIFO, each one enters the FIFO chain of registers. When you then read from the FIFO, the first data written (the "first in" part of FIFO) is the first data read out (the "first out" part of FIFO). Multiple writes do not overwrite previous data written, unless the FIFO is then full.

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