I'm working with dual ARM Corte-A9 in FPGA Zynq7000. I have three diferents hw with same software ( .elf and same files configuration linker script ). My problem is that SW works fine only in one hw (1 of 3). In other case, the processor halt in __libc_init_array function.
- The application runs in DDR PS memory (1023 MB)
- The aplication baseaddr is 0x100000
- In linker script, the stack size is 100 MB
The content of the __libc_init_array function is:
count = __preinit_array_end - __preinit_array_start;
for(i=0; i < count;i++)
coun = __init_array_end - __init_array_start;
for(i=0; i < count; i++)
__init_array_start[i](); // The ARM halt here when I = 10.
Can someone help me?
How can I debug this issue?
Why only works in one HW?
Thanks a lot.
Do you really use the same SW? Also the FSBL is the same? I'd recommend a JTAG debugger.
yes, is the same SW. I have tried both modes (QSPI and JTAG). The FSBL is the same but I have always tried JTAG debugger with empty memory flash and in this case, I don´t use the FSBL (I use the SDK scripts... ps7_init, ps7_post_config to initialize ARM).
So where exactly does it stop. With the debugger you should get the exact address.
What are the differences in the HW? Other DDRAM?
The three HW are identical and I have tested with industrialization test to check all components without any problem.
Linker script content;
.init_array: 0x0030af50 - 0x0030b1df
.fini_array: 0x0030b1e0 - 0x0030b1e3
.bss: 0x0030b1e8 - 0x02cb001f
.heap: 0x02cb0020 - 0x02cb201f
.stack: 0x02cb2020 - 0x0ccb381f
The assembler code is:
ldr r3, r4, #4
blx r3 The processor halt here when r4 is 0x0030af84 (address of .init_array)
When I read .init_array address, the content in both HW is the same:
30AF50: 00100504 30AF54: 0023C744 30AF58: 0023C774 30AF5C: 0023C7A4 30AF60: 0023C7D4 30AF64: 0023C804 30AF68: 0023C834 30AF6C: 0023C864 30AF70: 0023C894 30AF74: 0023C8C4 30AF78: 0023C9C0 30AF7C: 0023CA00 30AF80: 0023CA30 30AF84: 0023CB74 30AF88: 0023DD24
do you know what is the meaning of blx r3?
lammers7 said:do you know what is the meaning of blx r3?
See the TRM ;-)
.. do you know any way can I debug the issue with JTAG?
The problem was a bad initialization in array. SW is trying to read a PL memory address that It's not accesible before the entry of main.
For future reference:
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