SDRAM Window Boundary in MPU Address space in Cyclone V (Dual Cortex A9)

Hello!

The SDRAM starting and ending address in the MPU Address space is modifiable. The window can be enlarged or shrinked at the cost of BOOT ROM region and FPGA slaves region. It is written in TR-Manual that the total amount of SDRAM addressable from the other address spaces can be configured at run time. It could be done by writing into the address filtering start and end registers in the L2 cache controller ? right?

When we are writing the Scatter file for placing our code in the SDRAM, how can we beforehand know what's the SDRAM base address in MPU Address space? Can we change the SDRAM boundary window in the preloader, if yes how?

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