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How to configure a 10 inch TFT LCD in ARM Cortex-M3?

good evening to every one..i am new to this website..i want to know how to use 10 inch TFT display and LVDS colour formet??? can anyone help me..? thanks advance

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  • The flickering could also be because the sync polarity need to be changed.

    DE mode is "Display Enable" mode. That means that the Display Enable pin must be connected for this to work.

    You would also need to connect the DCLK signal.

    Using Google to search for TFT DE mode, I got some interesting results, especially LPC2000 results containg useful information.

    According to this page, both SYNC signals should be held low on the display.

    I also tried searching for a resolution and found a modeline, which could be interesting:

    Modeline "1024x600" 48.96 1024 1064 1168 1312 600 601 604 622 -hsync +vsync

    It seems this modeline is within your display's specifications.

    (You  can try using Google to search for the following words Modeline 1024 600 if you want more example resolutions)

    Now, to convert the modeline, you'll need to do some simple math...

    The first string mentioned in the "Modeline" is the name of the resolution: "1024x600"

    The next is a number, which is the PixelClock. This is 48.96 MHz.

    After that, we have the Horizontal Active Video, Front Porch, Sync Pulse and Back Porch.

    After those, we have the same for the Vertical direction.

    HAV = 1024

    HFP = (1064 - 1024): 40

    HSP = (1168 - 1064): 104

    HBP = (1312 - 1168): 144

    VAV = 600

    VFP = (601 - 600): 1

    VSP = (604 - 601): 3

    VBP = (622 - 604): 18

    Hsync pulse is negative.

    Vsync pulse is positive.

    I recommend trying the resolution first with DE mode disabled.

    If you have an oscilloscope (or a logic analyzer), I think it's important to measure that the HSync signal is correct.

    Also please verify that DCLK is running at 48.96 MHz.

    If it still flickers, you can try changing to DE mode.

    When using SYNC mode, please verify that DE is low all the time (DCLK is also unused, so I would expect it to be low).

    When using DE mode, please verify that both HSYNC and VSYNC are held low all the time.

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  • The flickering could also be because the sync polarity need to be changed.

    DE mode is "Display Enable" mode. That means that the Display Enable pin must be connected for this to work.

    You would also need to connect the DCLK signal.

    Using Google to search for TFT DE mode, I got some interesting results, especially LPC2000 results containg useful information.

    According to this page, both SYNC signals should be held low on the display.

    I also tried searching for a resolution and found a modeline, which could be interesting:

    Modeline "1024x600" 48.96 1024 1064 1168 1312 600 601 604 622 -hsync +vsync

    It seems this modeline is within your display's specifications.

    (You  can try using Google to search for the following words Modeline 1024 600 if you want more example resolutions)

    Now, to convert the modeline, you'll need to do some simple math...

    The first string mentioned in the "Modeline" is the name of the resolution: "1024x600"

    The next is a number, which is the PixelClock. This is 48.96 MHz.

    After that, we have the Horizontal Active Video, Front Porch, Sync Pulse and Back Porch.

    After those, we have the same for the Vertical direction.

    HAV = 1024

    HFP = (1064 - 1024): 40

    HSP = (1168 - 1064): 104

    HBP = (1312 - 1168): 144

    VAV = 600

    VFP = (601 - 600): 1

    VSP = (604 - 601): 3

    VBP = (622 - 604): 18

    Hsync pulse is negative.

    Vsync pulse is positive.

    I recommend trying the resolution first with DE mode disabled.

    If you have an oscilloscope (or a logic analyzer), I think it's important to measure that the HSync signal is correct.

    Also please verify that DCLK is running at 48.96 MHz.

    If it still flickers, you can try changing to DE mode.

    When using SYNC mode, please verify that DE is low all the time (DCLK is also unused, so I would expect it to be low).

    When using DE mode, please verify that both HSYNC and VSYNC are held low all the time.

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