I am currently working on Cortex A72 processor. I have generated hex file by compiling the c code file and asm file using Tizen compiler. The code consists of boot code for each core and each core starts executing its own code as soon as reset is deasserted. Core 0 is used to deassert reset of the other three cores. Each core starts executing from a common instruction address and each core is branched to the code meant for it using CPU ID.
I am monitoring the AXI Read transactions from the CPU (not the core). Core 0 starts fetching the instructions. As soon as reset of the other three cores is deasserted, they also start fetching the instruction using the same AXI read channel of the CPU. Due to this I am not able to know which AXI read transaction has been sent by which core.
So is there any way I can know which AXI read transaction has been generated by which core? Each core gives out the read address. Using this some idea can be taken. But I tried finding some address valid kind of signal from the core but had no success.
The Cortex-A72 TRM "ACE ARID and AWID assignment" chapter gives this kind of details, only for exclusive accesses.
AWID[1:0] is showing correct cpu core number but ARID[1:0] is not. When only core zero is active, ARID[1:0] goes from 0 to 1 and back to 0 with successive read transactions. When other cores wake up and start sending read transactions, ARID[1:0] is incorrect. Can you suggest anything?
Thanks and best regards,
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