how to understand L1 cache but L2 & L3 non-cached

A5.6.6 Memory Behavior
The Cortex-A55 core supports all the ARMv8 memory types.
However, the following behaviors are simplified and so for best performance their use is not recommended:
Write-Through

Memory that is marked as Write-Through cannot be cached on the data-side and does
not make coherency requests. On the instruction-side, areas that are marked as Write-
Through and Write-Back can be cached in the L1 instruction cache. However, only
areas marked as Write-Back can be cached in the L2 cache or the L3 cache.


Mixed inner and outer cacheability


Memory that is not marked as inner and outer Write-Back cannot be cached on the
data-side and does not make coherency requests. This applies to the memory type
only, and not to the allocation hints. All caches within the cluster are treated as being
part of the inner cacheability domain

Hi,

The .above description is reference to cortex a55 trm file.

1)However, only areas marked as Write-Back can be cached in the L2 cache or the L3 cache.

how to understand this  sentence? Does it mean that in this situation, the data and instruction cache from memory to L1 directly? How L1 access memory directly bypass L2?

2) This applies to the memory type only, and not to the allocation hints. 

Does it mean if support cache allocation, the data can also be cached?

Thanks