Store Buffer holds store operation before it is commited to Cache or Main Memory.
So only if the proper store buffer entry is drained, can we get the right data by a load operation. Am I right?
If yes, is it possible that we read a unexpected value after a write without a drain request(e.g. DMB)?
Which CPU? v7-M, R or A?
The reference manual for the CM7 says this:
5.8.2 Store buffer
"... The store buffer is drained of all stores to Strongly-ordered or Device memory before a load is performed from Strongly-ordered or Device memory."
But interestingly, nothing can be found about read from normal memory ...
Actually, I know for normal memory store buffer is drained when the entry is full or the entry has been waiting for long enough.
I have no idea if the CPU can scan its own store buffer for a read and if a wrong data will be got before the store buffer entry is drained.
Yang Wang said:if a wrong data will be got before the store buffer entry is drained
On a single cpu, the sequence of instructions,
a = 1;r = a;
is expected by the programmer to end with r set to 1, regardless of the presence or absence of store buffer. With the store buffer, an implementation may choose to read from it, or wait until the store is drain and then fetch from beyond the cpu.
For shared-memory multiprocessors, use of barriers as advised in the manuals help the programmer avoid the need to know about the store buffer.
OK. Thanks very much.
So you mean that on a single cpu, whether store buffer is presence or absence and whether read from stroe buffer or waiting for store buffer drained during a load operation are both implemention defined. Is my understanding right?
That is correct, on both single- and multi- processors.
The single cpu reference was to highlight, through an example, that a cpu won't return wrong data as you feared (in the particular case of a cpu reading its own writes to a location not shared with other cpus).
Edit: For clarity.
OK, thank you very much!