[NUCLEO-F031K6试用]MDK寄存器版：1、点灯

之前一直没有时间搞这块Mini的板子，现在抽出时间了。下面分享一下我的成果。

程序效果需要在仿真的时候才能出现，请在Debug模式下设置断电后，单步调试实现LED指示灯的亮灭。

代码如下：

mian.c

#include "stm32f0xx.h"
#include "sys.h"
#include "led.h"


int main(void)
{
  SystemCoreClockConfigure();
  SystemCoreClockUpdate();
  led_init();
  while(1)
  {
  GPIOB->BSRR = 0x1 << 3;
  GPIOB->BRR = 0x1 << 3;
  }
}

led.c

#include "led.h"


int
  led_init(void)
{
  //PB3
  RCC->AHBENR |= 0x00040000;

  GPIOB->MODER &= ~(0x3 << 6);
  GPIOB->MODER |= 0x1 << 6;
  GPIOB->OTYPER &= ~(0x1 << 3);
  GPIOB->OSPEEDR |= 0x3 << 6;
  GPIOB->PUPDR &= ~(0x3 << 6);
  GPIOB->AFR[0] |= 0x3 << (3 * 4);
  return 0;
}

sys.c

#include "sys.h"


/*----------------------------------------------------------------------------
 * SystemCoreClockConfigure: configure SystemCoreClock using HSI
 *----------------------------------------------------------------------------*/
void SystemCoreClockConfigure(void) {


  RCC->CR |= ((uint32_t)RCC_CR_HSION);                     // Enable HSI
  while ((RCC->CR & RCC_CR_HSIRDY) == 0);                  // Wait for HSI Ready


  RCC->CFGR = RCC_CFGR_SW_HSI;                             // HSI is system clock
  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI);  // Wait for HSI used as system clock


  FLASH->ACR  = FLASH_ACR_PRFTBE;                          // Enable Prefetch Buffer
  FLASH->ACR |= FLASH_ACR_LATENCY;                         // Flash 1 wait state


  RCC->CFGR |= RCC_CFGR_HPRE_DIV1;                         // HCLK = SYSCLK
  RCC->CFGR |= RCC_CFGR_PPRE_DIV1;                         // PCLK = HCLK


  RCC->CR &= ~RCC_CR_PLLON;                                // Disable PLL


  //  PLL configuration:  = HSI/2 * 12 = 48 MHz
  RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL);
  RCC->CFGR |=  (RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLMULL12);


  RCC->CR |= RCC_CR_PLLON;                                 // Enable PLL
  while((RCC->CR & RCC_CR_PLLRDY) == 0) __NOP();           // Wait till PLL is ready


  RCC->CFGR &= ~RCC_CFGR_SW;                               // Select PLL as system clock source
  RCC->CFGR |=  RCC_CFGR_SW_PLL;
  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL);  // Wait till PLL is system clock src
}

工程模板附件如下：