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  • Description The latest forum discussions for community-based support for System-on-Chip (SoC) and Arm simulation models.
  • Threads 729 Questions
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  • Not Answered

    HTRANS when HREADY is low on the 2nd HCLK after starting the transfer 0

    • AMBA 3 AHB Interface
    • AHB
    4462 views
    1 reply
    Latest over 4 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    Keil_v5 stopped recognizing Segger debugger 0

    1117 views
    0 replies
    Started over 4 years ago
    by bptsj
  • Answered

    AMBA TLM 2.0 Library & AMBA-PV Extensions to TLM +1

    7304 views
    3 replies
    Latest over 4 years ago
    by Toshihisa Oishi Arm Employee Badge
  • Not Answered

    Does CoreSight support ThunderX2 server? 0

    • CoreSight
    3559 views
    0 replies
    Started over 4 years ago
    by hi-watanabe
  • Not Answered

    DATABASE STC-STC12 COULDN'T FIND IN SELECT DEVICE FOR TARGET WHEN IT POP UP 0

    1131 views
    0 replies
    Started over 4 years ago
    by miee
  • Answered

    simuating assembly code in qemu +1

    1960 views
    1 reply
    Latest over 4 years ago
    by Ronan Synnott Arm Employee Badge
  • Not Answered

    AHB two-cycle Response +1

    7476 views
    1 reply
    Latest over 4 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    In APB, for data bus width, can I increase from 32 bits(default) to 64 bits(as per my project requirements)? 0

    • APB
    • AMBA 2 APB Interface
    10373 views
    1 reply
    Latest over 4 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    what is "transfer" signal mentioned in the APB state diagram? Can I use "PSELx" signal to determine transfer is going to happen? 0

    • APB
    • AMBA 2 APB Interface
    7600 views
    1 reply
    Latest over 4 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    Can secure states know that they are in secure state? 0

    6975 views
    0 replies
    Started over 4 years ago
    by chenyinhua
  • Not Answered

    L4 cache in N1 SDP SoC 0

    8061 views
    2 replies
    Latest over 4 years ago
    by Oliver Beirne Arm Employee Badge
  • Not Answered

    test cases for apb 0

    14987 views
    4 replies
    Latest over 4 years ago
    by Antonetta
  • Answered

    Number of masters/slaves in AHB 0

    10970 views
    1 reply
    Latest over 4 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Model debugger unstable when attempt to load more than one target +1

    3251 views
    3 replies
    Latest over 4 years ago
    by CDAMP
  • Not Answered

    L1 cache BW 0

    8113 views
    2 replies
    Latest over 4 years ago
    by Robert Wolff
  • Answered

    In AXI Why there is a read response in each data transfer? 0

    22491 views
    3 replies
    Latest over 4 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    C9912E: --cpu selected +1

    10596 views
    1 reply
    Latest over 4 years ago
    by Christiana
  • Not Answered

    AXI interconnect performance improvement 0

    8899 views
    1 reply
    Latest over 4 years ago
    by Colin Campbell Arm Employee Badge
  • Not Answered

    ICODE and DCODE Fetches 0

    • Cortex-M3
    8253 views
    0 replies
    Started over 5 years ago
    by eugch
  • Answered

    USB not detected 0

    4120 views
    4 replies
    Latest over 5 years ago
    by DRsecr
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