Would you please help me to understand why every slaves always hreadyout declared as '1' in Cortex M Design Kit and can't modify it in slave status?
I found a declaration assign hreadyouts = 1'b1;
Actually I'm trying to monitor only HWDATA and HRDATA when they are executed as the below
As you can see the above waveform, there are 4 HWDATA and 4HRDATA . But there is no way what I want to capture the only executed point. because Hready is always '1' and else signals also doesn't help much to me.
Could you guide me how I can check the only read and write event for HRDATA and HWDATA ?
Unfortunately you didn't answer my question about where in CMSDK you are looking, so I'm still not sure what you are asking about.
From your latest question, if I understand it correctly you are either worried about a delay from the data phase starting to when HRDATA can be sampled on an HCLK rising edge by the master, or else you are worried about meeting single cycle timing for a long path on HRDATA from the slave back to the master.
If it is the HRDATA not reaching the master in time to meet the next HCLK rising edge timing, the slave will have to add a wait state on HREADY.
If you are concerned about a long timing path on HRDATA, you can't just add a register to this path as that will break the relationship between address and data phases of a transfer, so you would need to add an AHB to AHB bridge between the master and slave, and this would then break the long timing path (at a cost of latency).
Sorry, I'm not sure what the BUSY cycle is that you are referring to.
Thank you Colin,
Yes, actually I was concerning that long timing path on HRDATA, But I am clear Now.
Thank you Colin again and sorry for late,