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Is AHB Slave need sample HREADY on data phase?

Lumi Yang

Hello,

I have a question on simple system as below : Two master and Two slave

For HREADYOUT at Slave, it's can extend "data phase" by "LOW" if can't provide or sample the data.

For HREADY at Master, it's drive by multiplexor, it's means that the transfer is not completed if HREADY is "LOW", and the transfer must be extend.

For slaves, what is the meaning of "HREADY" on address phase and data phase? 

If Slave 1 is providing the data phase of last burst transfer of Master 1,  and Master 1 is send new transfer to Slave 2 in same time.

But Slave 2 is serving Master 2 now(extend data phase), so "HREADY" is "LOW" on Slave 1 and Master 1? or HREADY, HTRANS, HADDR,... is share bus on Multi-Master AHB system, so this case is impossible?

Thanks a lot

Parents
  • 0 in reply to Lumi Yang
    Lumi Yang said:
    So in the Multi-Layer AHB Bus Matrix, it must be can store the address and control signal in this case

    Yes, the input stage must store the address and control signals in this case. The address phase cannot be prolonged when the HREADY is HIGH from Master 1’s side, hence the address phase of Master 1 will end and the address and control signals must be stored in Input Stage.

    Lumi Yang said:
    must judge who have high priority

    This depends on your design. The priority of Master 1 (Layer 1) or Master 2 (Layer 2) is decided by the design of arbiters of each Slave. Hence, you can set Layer 1 to be prioritized than Layer 2, or you can just let the transfer that happens earlier be prioritized.

    Lumi Yang said:
    driving HREADY to all relevant Master and Slave

    Yes, the HREADY signal must be driven to all relevant Masters and Slaves.

Reply
  • 0 in reply to Lumi Yang
    Lumi Yang said:
    So in the Multi-Layer AHB Bus Matrix, it must be can store the address and control signal in this case

    Yes, the input stage must store the address and control signals in this case. The address phase cannot be prolonged when the HREADY is HIGH from Master 1’s side, hence the address phase of Master 1 will end and the address and control signals must be stored in Input Stage.

    Lumi Yang said:
    must judge who have high priority

    This depends on your design. The priority of Master 1 (Layer 1) or Master 2 (Layer 2) is decided by the design of arbiters of each Slave. Hence, you can set Layer 1 to be prioritized than Layer 2, or you can just let the transfer that happens earlier be prioritized.

    Lumi Yang said:
    driving HREADY to all relevant Master and Slave

    Yes, the HREADY signal must be driven to all relevant Masters and Slaves.

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