Hello,
I have a question on simple system as below : Two master and Two slave
For HREADYOUT at Slave, it's can extend "data phase" by "LOW" if can't provide or sample the data.
For HREADY at Master, it's drive by multiplexor, it's means that the transfer is not completed if HREADY is "LOW", and the transfer must be extend.
For slaves, what is the meaning of "HREADY" on address phase and data phase?
If Slave 1 is providing the data phase of last burst transfer of Master 1, and Master 1 is send new transfer to Slave 2 in same time.
But Slave 2 is serving Master 2 now(extend data phase), so "HREADY" is "LOW" on Slave 1 and Master 1? or HREADY, HTRANS, HADDR,... is share bus on Multi-Master AHB system, so this case is impossible?
Thanks a lot
The HREADY signal to AHB slave is used to determine whether the data phase of the previous transfer is completed. A slave will sample the address and other control signals only when both HSEL and HREADY are HIGH. It is explained in AHB spec at developer.arm.com/.../bb:
When HIGH, the HREADY signal indicates to the master and all slaves, that the previous transfer is complete.
Here is the multiplexor diagram in a single layer AHB bus for your reference:
The HREADY for each layer, is made of the HREADYOUT of the slave currently in data phase.
Back to your question
Lumi Yang said:But Slave 2 is serving Master 2 now(extend data phase), so "HREADY" is "LOW" on Slave 1 and Master 1?
When Slave 2 is serving Master 2, in the cycle you mentioned, while Slave 1 is providing the data phase of last burst transfer of Master 1, HREADY should be high for Master 1 and Slave 1, since HREADY of Master 1 is mapped to the HREADYOUT of Slave 1 in this cycle.
In the next cycle, if Slave 2 is still serving Master 2, HREADY will be low to Master 1, so Master 1 will be waited.
Here is the explanation of this situation in Multi-layer AHB overview at developer.arm.com/.../b:
If two layers require access to the same slave at the same time, the arbitration within the interconnect matrix must determine which layer has highest priority. The layer that is not given access is waited using HREADY until it is given access to the required slave.
When a layer is waited an Input Stage is used to store a copy of the pipelined address and control information until the access to the shared slave is given.
So in the Multi-Layer AHB Bus Matrix, it must be can store the address and control signal in this case, and must judge who have high priority, and driving HREADY to all relevant Master and Slave?
Lumi Yang said:So in the Multi-Layer AHB Bus Matrix, it must be can store the address and control signal in this case
Yes, the input stage must store the address and control signals in this case. The address phase cannot be prolonged when the HREADY is HIGH from Master 1’s side, hence the address phase of Master 1 will end and the address and control signals must be stored in Input Stage.
Lumi Yang said:must judge who have high priority
This depends on your design. The priority of Master 1 (Layer 1) or Master 2 (Layer 2) is decided by the design of arbiters of each Slave. Hence, you can set Layer 1 to be prioritized than Layer 2, or you can just let the transfer that happens earlier be prioritized.
Lumi Yang said:driving HREADY to all relevant Master and Slave
Yes, the HREADY signal must be driven to all relevant Masters and Slaves.
Thanks for your answer.