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Hello, Using an LPC2400 family with UART FIFOs enabled (RX & RX) does this mean that in entire TX FIFO (16 bytes) must be filled in order to have data placed on the bus, or does that happen every predefined period? I looked in the data sheet of the processor and the UART itself to no avail...
You don't need to fill the transmit FIFO full to start transmitting. It will automatically transmit.
There is a bit of special logic that will delay the THRE interrupt to give you time to fill in more characters in the FIFO. After you have had at least two characters in the TX FIFO at the same time, the next THRE will come immediately, to inform you that the TX FIFO needs more data.
I understand - thanks. sorry for asking, I never worked with a FIFO UART before (only not FIFOed). anyway, the data sheet says this:
A THRE interrupt is set immediately if the UARTn THR FIFO has held two or more characters at one time and currently, the UnTHR is empty.
what does that mean if I need to place a buffer of, say, 1000 bytes on the bus? how do I get that done smoothly?
You write your UART interrupt so that if it sees the THRE flag, you do multiple inserts into the transmit holding register. If you add 16 characters for every THRE interrupt, the load on the processor will be significantly lower than running without the FIFO.
ok, I can poll bit6 in line status register, which indicated both the holding register and the short register empty (hence, the THRE interrupt is not necessary). then I can place 16 bytes in hardware, not?
yes of course, I understand what you mean. thanks a lot.
If you wait until you get a TEMT (Transmitter empty) then your UART will stop while waiting for more food. It is better that you start filling it when you see the THRE bit - that means that the last byte of the FIFO has been moved into the outgoing shift register and you now have one character time period to start adding more data to not get a stalled transmitter.
Is there any reason why you prefer a loop to poll the status instead of just using a ring buffer and have an interrupt react and refill the FIFO?
I am sorry for bothering you again, but I still don't understand precisely what the THRE interrupt is all about: If I read the documentation, I understand that it means that there is room for more data (1 byte at least?). so, how can I pump data into it without knowing the condition of the shift register? isn't it so that the shift register is 16 bytes in size? the THR is merely a register; what is the FIFO only has 1 free slot when the THRE interrupt occured? thanks.
ho sorry - the FIFO and the shift register are separate entities! ok now I get it. thanks.