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Hello, Using an LPC2400 family with UART FIFOs enabled (RX & RX) does this mean that in entire TX FIFO (16 bytes) must be filled in order to have data placed on the bus, or does that happen every predefined period? I looked in the data sheet of the processor and the UART itself to no avail...
I am sorry for bothering you again, but I still don't understand precisely what the THRE interrupt is all about: If I read the documentation, I understand that it means that there is room for more data (1 byte at least?). so, how can I pump data into it without knowing the condition of the shift register? isn't it so that the shift register is 16 bytes in size? the THR is merely a register; what is the FIFO only has 1 free slot when the THRE interrupt occured? thanks.