Hello, Using an LPC2400 family with UART FIFOs enabled (RX & RX) does this mean that in entire TX FIFO (16 bytes) must be filled in order to have data placed on the bus, or does that happen every predefined period? I looked in the data sheet of the processor and the UART itself to no avail...
You write your UART interrupt so that if it sees the THRE flag, you do multiple inserts into the transmit holding register. If you add 16 characters for every THRE interrupt, the load on the processor will be significantly lower than running without the FIFO.
yes of course, I understand what you mean. thanks a lot.
I am sorry for bothering you again, but I still don't understand precisely what the THRE interrupt is all about: If I read the documentation, I understand that it means that there is room for more data (1 byte at least?). so, how can I pump data into it without knowing the condition of the shift register? isn't it so that the shift register is 16 bytes in size? the THR is merely a register; what is the FIFO only has 1 free slot when the THRE interrupt occured? thanks.