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Hello, Using an LPC2400 family with UART FIFOs enabled (RX & RX) does this mean that in entire TX FIFO (16 bytes) must be filled in order to have data placed on the bus, or does that happen every predefined period? I looked in the data sheet of the processor and the UART itself to no avail...
If you wait until you get a TEMT (Transmitter empty) then your UART will stop while waiting for more food. It is better that you start filling it when you see the THRE bit - that means that the last byte of the FIFO has been moved into the outgoing shift register and you now have one character time period to start adding more data to not get a stalled transmitter.
Is there any reason why you prefer a loop to poll the status instead of just using a ring buffer and have an interrupt react and refill the FIFO?
ho sorry - the FIFO and the shift register are separate entities! ok now I get it. thanks.