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Hello, Using an LPC2400 family with UART FIFOs enabled (RX & RX) does this mean that in entire TX FIFO (16 bytes) must be filled in order to have data placed on the bus, or does that happen every predefined period? I looked in the data sheet of the processor and the UART itself to no avail...
ho sorry - the FIFO and the shift register are separate entities! ok now I get it. thanks.