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L2 cache configuration

George Palathingal
Note: This was originally posted on 20th April 2011 at http://forums.arm.com

Hello guys,

           Anybody here knows what is default size of ARM Cortex-A8 L2 cache as it is given in the manual that it can be from 0kb to 1 mb.How to resize the L2 cache according to our needs.I tried reading the cp15 register using MRC but it is throwing "Illegal instruction" run time error.I suppose I need to be supervisor mode to access the coprocessor registers.Can any body help me with these issues ??

Thanks in advance,
  • Note: This was originally posted on 21st April 2011 at http://forums.arm.com


    The L2 cache size if fixed for a specific design ... it's part of the hardware layout so cannot be changed. Different chip designs can have different sizes though.

    Any yes, you need privileged access to read the register.



    Hello isogen74,

    First of all, thank you for your response.But I am not talking about the physical size of L2 cache.My question is , as per the reference manual for Cortex A8 L2 cache can be configured to use from 0KB to 1Mb only for data using CSSR register.How can I access this register as a privilaged user so that I configure it as per my needs or is that possible ??
  • Note: This was originally posted on 26th April 2011 at http://forums.arm.com

    Thank you very much...

    A few more questions

    In CSIR once the level is selected from CSSR, the only thing that differentiates the sizes is 'Numsets'.Where does the processor get this value from ?
    &
    Will the size of the L2 cache change dynamically or will it remain static once it is set on reset ( because the value of these registers seem to be 'unpredictable on reset' from the manual ) & if it is static what will be default size of L2 cache ?

    I am actually trying to optimize an application on Arm cortex A-8.As I am almost done with code level optimization I am trying to find if I can get any support from processor to improve the performance(I am already done with NEON).
  • Arm Employee Badge
    Note: This was originally posted on 20th April 2011 at http://forums.arm.com

    The L2 cache size if fixed for a specific design ... it's part of the hardware layout so cannot be changed. Different chip designs can have different sizes though.

    Any yes, you need privileged access to read the register.

  • Arm Employee Badge
    Note: This was originally posted on 21st April 2011 at http://forums.arm.com

    These register's don't modify the cache setup ...

    There are two sets of registers:

       CSSR - the cache size selection register
       CSIR - the cache size identification register

    The same CSIR instruction is used for all of the caches which are "architecturally integrated" - the L1 and the L2 in the Cortex-A8 case. You write a cache level into the CSSR to select which cache's data is returned by the CSIR. But the CSIR itself is read-only.

    Iso
  • Arm Employee Badge
    Note: This was originally posted on 26th April 2011 at http://forums.arm.com

    [color=#222222][size=2]
    [color=#222222][size=2]It will be a static size for each chip design; it is decided when the silicon is laid out ... [/size][/color]
    [color=#222222][size=2]
    [/size][/color]>> what will be default size of L2 cache?[/size][/color]
    [color=#222222][size=2]
    [/size][/color]
    [color=#222222][size=2]There is no default size - each chip manufacturer decides what sizes to put in the chip, but will typically something like [/size][/color][color=#222222][size=2]32KB L1 I and D caches, and 256KB per core for L2. Older ARM cores, such as ARM11, will typically have smaller caches - but as you mention NEON I assume you are only interested in the Cortex-A* cores.[/size][/color]