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L2 cache configuration

George Palathingal
Note: This was originally posted on 20th April 2011 at http://forums.arm.com

Hello guys,

           Anybody here knows what is default size of ARM Cortex-A8 L2 cache as it is given in the manual that it can be from 0kb to 1 mb.How to resize the L2 cache according to our needs.I tried reading the cp15 register using MRC but it is throwing "Illegal instruction" run time error.I suppose I need to be supervisor mode to access the coprocessor registers.Can any body help me with these issues ??

Thanks in advance,
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  • Note: This was originally posted on 21st April 2011 at http://forums.arm.com


    The L2 cache size if fixed for a specific design ... it's part of the hardware layout so cannot be changed. Different chip designs can have different sizes though.

    Any yes, you need privileged access to read the register.



    Hello isogen74,

    First of all, thank you for your response.But I am not talking about the physical size of L2 cache.My question is , as per the reference manual for Cortex A8 L2 cache can be configured to use from 0KB to 1Mb only for data using CSSR register.How can I access this register as a privilaged user so that I configure it as per my needs or is that possible ??
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  • Note: This was originally posted on 21st April 2011 at http://forums.arm.com


    The L2 cache size if fixed for a specific design ... it's part of the hardware layout so cannot be changed. Different chip designs can have different sizes though.

    Any yes, you need privileged access to read the register.



    Hello isogen74,

    First of all, thank you for your response.But I am not talking about the physical size of L2 cache.My question is , as per the reference manual for Cortex A8 L2 cache can be configured to use from 0KB to 1Mb only for data using CSSR register.How can I access this register as a privilaged user so that I configure it as per my needs or is that possible ??
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