• Locked Locked
  • Replies 5 replies
  • Subscribers 118 subscribers
  • Views 3880 views
  • Users 0 members are here
Options
Related
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

L2 cache configuration

George Palathingal
Note: This was originally posted on 20th April 2011 at http://forums.arm.com

Hello guys,

           Anybody here knows what is default size of ARM Cortex-A8 L2 cache as it is given in the manual that it can be from 0kb to 1 mb.How to resize the L2 cache according to our needs.I tried reading the cp15 register using MRC but it is throwing "Illegal instruction" run time error.I suppose I need to be supervisor mode to access the coprocessor registers.Can any body help me with these issues ??

Thanks in advance,
Parents
  • Arm Employee Badge
    Note: This was originally posted on 21st April 2011 at http://forums.arm.com

    These register's don't modify the cache setup ...

    There are two sets of registers:

       CSSR - the cache size selection register
       CSIR - the cache size identification register

    The same CSIR instruction is used for all of the caches which are "architecturally integrated" - the L1 and the L2 in the Cortex-A8 case. You write a cache level into the CSSR to select which cache's data is returned by the CSIR. But the CSIR itself is read-only.

    Iso
Reply
  • Arm Employee Badge
    Note: This was originally posted on 21st April 2011 at http://forums.arm.com

    These register's don't modify the cache setup ...

    There are two sets of registers:

       CSSR - the cache size selection register
       CSIR - the cache size identification register

    The same CSIR instruction is used for all of the caches which are "architecturally integrated" - the L1 and the L2 in the Cortex-A8 case. You write a cache level into the CSSR to select which cache's data is returned by the CSIR. But the CSIR itself is read-only.

    Iso
Children
No data