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L2 cache configuration

George Palathingal
Note: This was originally posted on 20th April 2011 at http://forums.arm.com

Hello guys,

           Anybody here knows what is default size of ARM Cortex-A8 L2 cache as it is given in the manual that it can be from 0kb to 1 mb.How to resize the L2 cache according to our needs.I tried reading the cp15 register using MRC but it is throwing "Illegal instruction" run time error.I suppose I need to be supervisor mode to access the coprocessor registers.Can any body help me with these issues ??

Thanks in advance,
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  • Note: This was originally posted on 26th April 2011 at http://forums.arm.com

    Thank you very much...

    A few more questions

    In CSIR once the level is selected from CSSR, the only thing that differentiates the sizes is 'Numsets'.Where does the processor get this value from ?
    &
    Will the size of the L2 cache change dynamically or will it remain static once it is set on reset ( because the value of these registers seem to be 'unpredictable on reset' from the manual ) & if it is static what will be default size of L2 cache ?

    I am actually trying to optimize an application on Arm cortex A-8.As I am almost done with code level optimization I am trying to find if I can get any support from processor to improve the performance(I am already done with NEON).
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  • Note: This was originally posted on 26th April 2011 at http://forums.arm.com

    Thank you very much...

    A few more questions

    In CSIR once the level is selected from CSSR, the only thing that differentiates the sizes is 'Numsets'.Where does the processor get this value from ?
    &
    Will the size of the L2 cache change dynamically or will it remain static once it is set on reset ( because the value of these registers seem to be 'unpredictable on reset' from the manual ) & if it is static what will be default size of L2 cache ?

    I am actually trying to optimize an application on Arm cortex A-8.As I am almost done with code level optimization I am trying to find if I can get any support from processor to improve the performance(I am already done with NEON).
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