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L2 cache configuration

George Palathingal
Note: This was originally posted on 20th April 2011 at http://forums.arm.com

Hello guys,

           Anybody here knows what is default size of ARM Cortex-A8 L2 cache as it is given in the manual that it can be from 0kb to 1 mb.How to resize the L2 cache according to our needs.I tried reading the cp15 register using MRC but it is throwing "Illegal instruction" run time error.I suppose I need to be supervisor mode to access the coprocessor registers.Can any body help me with these issues ??

Thanks in advance,
Parents
  • Arm Employee Badge
    Note: This was originally posted on 26th April 2011 at http://forums.arm.com

    [color=#222222][size=2]
    [color=#222222][size=2]It will be a static size for each chip design; it is decided when the silicon is laid out ... [/size][/color]
    [color=#222222][size=2]
    [/size][/color]>> what will be default size of L2 cache?[/size][/color]
    [color=#222222][size=2]
    [/size][/color]
    [color=#222222][size=2]There is no default size - each chip manufacturer decides what sizes to put in the chip, but will typically something like [/size][/color][color=#222222][size=2]32KB L1 I and D caches, and 256KB per core for L2. Older ARM cores, such as ARM11, will typically have smaller caches - but as you mention NEON I assume you are only interested in the Cortex-A* cores.[/size][/color]
Reply
  • Arm Employee Badge
    Note: This was originally posted on 26th April 2011 at http://forums.arm.com

    [color=#222222][size=2]
    [color=#222222][size=2]It will be a static size for each chip design; it is decided when the silicon is laid out ... [/size][/color]
    [color=#222222][size=2]
    [/size][/color]>> what will be default size of L2 cache?[/size][/color]
    [color=#222222][size=2]
    [/size][/color]
    [color=#222222][size=2]There is no default size - each chip manufacturer decides what sizes to put in the chip, but will typically something like [/size][/color][color=#222222][size=2]32KB L1 I and D caches, and 256KB per core for L2. Older ARM cores, such as ARM11, will typically have smaller caches - but as you mention NEON I assume you are only interested in the Cortex-A* cores.[/size][/color]
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