You say you get an abort, what does the IFSR and IFAR say?
/* 273 * Invalidate L1 I/D 274 */ 275 mov r0, #0 @ set up for MCR 276 mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs 277 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache 278 279 /* 280 * disable MMU stuff and caches 281 */ 282 mrc p15, 0, r0, c1, c0, 0 283 bic r0, r0, #0x00002000 @ clear bits 13 (--V-) 284 bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) 285 orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align 286 orr r0, r0, #0x00000800 @ set bit 12 (Z---) BTB 287 mcr p15, 0, r0, c1, c0, 0
277 mcr p15, 0, r0, c7, c5, 0 @ invalidate icache
Cache memory needs to be invalidated before it is being used or initialized.
Kindly go through the following steps :
1. Clean and invalidate cache memory
2. NOP for certain clock cycles as specified by TRM
3. Initialize the I cache and D cache
4. ISB / DSB should be executed.
The above steps should be carried out for both L1 and L2 cache memory.