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Enabling I-cache resulting into an abort

Note: This was originally posted on 17th November 2010 at http://forums.arm.com

Hi,

I am working on a bootloader for Cortex-A8 based on the open source bootloader U-Boot v2010.06. I have a 2 stage approach where the 1st stage boots up, loads the 2nd stage to DDR and then passes control to it.

Things work fine without cache enabled in the 1st stage. However when i enable the I-cache in the 1st stage and transfer control to the second stage, the 2nd stage runs for a few instructions and then goes into an abort in a perfectly valid instruction.

What is even more puzzling is that leaving the cache ON seems to affect only a particular boot mode. When the 2 stages are fetched from NAND or UART there is no problem. But when i use SD card for loading the 2 stages this problem crops up.

I even tried putting the Instruction Sync Barrier instruction before the jump to the code where the abort occurs... but no change.

Any pointers?

Thanks,
Vaibhav

P.S.: I could attach the code snippet for this if it helps

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Martin Weidmann over 12 years ago

Note: This was originally posted on 18th November 2010 at http://forums.arm.com

Most ARM cores have registers to give information on the cause of an abort, which you can read within your abort handlers. These are:

- Fault Status Register - Type of abort (e.g. from the MMU, from external memory, unaligned access, ....)
- Fault Address Register - The actual address that aborted

There are usually separate registers for data aborts (DFSR and DFAR) and prefectch aborts (IFSR and IFAR). So if you are getting a prefetch abort, a good place to start is the contents of these registers.

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344b/Bgbjhija.html - IFSR
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344b/Babcjgia.html - IFAR
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Martin Weidmann over 12 years ago

Note: This was originally posted on 18th November 2010 at http://forums.arm.com

Most ARM cores have registers to give information on the cause of an abort, which you can read within your abort handlers. These are:

- Fault Status Register - Type of abort (e.g. from the MMU, from external memory, unaligned access, ....)
- Fault Address Register - The actual address that aborted

There are usually separate registers for data aborts (DFSR and DFAR) and prefectch aborts (IFSR and IFAR). So if you are getting a prefetch abort, a good place to start is the contents of these registers.

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344b/Bgbjhija.html - IFSR
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0344b/Babcjgia.html - IFAR
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