• Locked Locked
  • Replies 7 replies
  • Subscribers 119 subscribers
  • Views 4927 views
  • Users 0 members are here
2025 survey

We are running a survey to help us improve the experience for all of our members. If you see the survey appear, please take the time to tell us about your experience if you can.

Options
Related
How was your experience today?
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Enabling I-cache resulting into an abort

Vaibhav Bedia
Note: This was originally posted on 17th November 2010 at http://forums.arm.com

Hi,

I am working on a bootloader for Cortex-A8 based on the open source bootloader U-Boot v2010.06. I have a 2 stage approach where the 1st stage boots up, loads the 2nd stage to DDR and then passes control to it.

Things work fine without cache enabled in the 1st stage. However when i enable the I-cache in the 1st stage and transfer control to the second stage, the 2nd stage runs for a few instructions and then goes into an abort in a perfectly valid instruction.

What is even more puzzling is that leaving the cache ON seems to affect only a particular boot mode. When the 2 stages are fetched from NAND or UART there is no problem. But when i use SD card for loading the 2 stages this problem crops up.

I even tried putting the Instruction Sync Barrier instruction before the jump to the code where the abort occurs... but no change.

Any pointers?

Thanks,
Vaibhav

P.S.: I could attach the code snippet for this if it helps
Parents

  • Cache memory needs to be invalidated before it is being used or initialized.

    Kindly go through the following steps :

    1. Clean and invalidate cache memory

    2. NOP for certain clock cycles as specified by TRM

    3. Initialize the I cache and D cache

    4. ISB / DSB should be executed.

    The above steps should be carried out for both L1 and L2 cache memory.

Reply

  • Cache memory needs to be invalidated before it is being used or initialized.

    Kindly go through the following steps :

    1. Clean and invalidate cache memory

    2. NOP for certain clock cycles as specified by TRM

    3. Initialize the I cache and D cache

    4. ISB / DSB should be executed.

    The above steps should be carried out for both L1 and L2 cache memory.

Children
No data