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Enabling I-cache resulting into an abort

Vaibhav Bedia
Note: This was originally posted on 17th November 2010 at http://forums.arm.com

Hi,

I am working on a bootloader for Cortex-A8 based on the open source bootloader U-Boot v2010.06. I have a 2 stage approach where the 1st stage boots up, loads the 2nd stage to DDR and then passes control to it.

Things work fine without cache enabled in the 1st stage. However when i enable the I-cache in the 1st stage and transfer control to the second stage, the 2nd stage runs for a few instructions and then goes into an abort in a perfectly valid instruction.

What is even more puzzling is that leaving the cache ON seems to affect only a particular boot mode. When the 2 stages are fetched from NAND or UART there is no problem. But when i use SD card for loading the 2 stages this problem crops up.

I even tried putting the Instruction Sync Barrier instruction before the jump to the code where the abort occurs... but no change.

Any pointers?

Thanks,
Vaibhav

P.S.: I could attach the code snippet for this if it helps
Parents
  • Note: This was originally posted on 18th November 2010 at http://forums.arm.com

    Yes. The cache is invalidated before being enabled.


    /*
    273       * Invalidate L1 I/D
    274       */
    275   mov  r0, #0               @ set up for MCR
    276   mcr  p15, 0, r0, c8, c7, 0   @ invalidate TLBs
    277   mcr  p15, 0, r0, c7, c5, 0   @ invalidate icache
    278
    279   /*
    280       * disable MMU stuff and caches
    281       */
    282   mrc  p15, 0, r0, c1, c0, 0
    283   bic  r0, r0, #0x00002000  @ clear bits 13 (--V-)
    284   bic  r0, r0, #0x00000007  @ clear bits 2:0 (-CAM)
    285   orr  r0, r0, #0x00000002  @ set bit 1 (--A-) Align
    286   orr  r0, r0, #0x00000800  @ set bit 12 (Z---) BTB
    287   mcr  p15, 0, r0, c1, c0, 0
Reply
  • Note: This was originally posted on 18th November 2010 at http://forums.arm.com

    Yes. The cache is invalidated before being enabled.


    /*
    273       * Invalidate L1 I/D
    274       */
    275   mov  r0, #0               @ set up for MCR
    276   mcr  p15, 0, r0, c8, c7, 0   @ invalidate TLBs
    277   mcr  p15, 0, r0, c7, c5, 0   @ invalidate icache
    278
    279   /*
    280       * disable MMU stuff and caches
    281       */
    282   mrc  p15, 0, r0, c1, c0, 0
    283   bic  r0, r0, #0x00002000  @ clear bits 13 (--V-)
    284   bic  r0, r0, #0x00000007  @ clear bits 2:0 (-CAM)
    285   orr  r0, r0, #0x00000002  @ set bit 1 (--A-) Align
    286   orr  r0, r0, #0x00000800  @ set bit 12 (Z---) BTB
    287   mcr  p15, 0, r0, c1, c0, 0
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