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Enabling I-cache resulting into an abort

Vaibhav Bedia
Note: This was originally posted on 17th November 2010 at http://forums.arm.com

Hi,

I am working on a bootloader for Cortex-A8 based on the open source bootloader U-Boot v2010.06. I have a 2 stage approach where the 1st stage boots up, loads the 2nd stage to DDR and then passes control to it.

Things work fine without cache enabled in the 1st stage. However when i enable the I-cache in the 1st stage and transfer control to the second stage, the 2nd stage runs for a few instructions and then goes into an abort in a perfectly valid instruction.

What is even more puzzling is that leaving the cache ON seems to affect only a particular boot mode. When the 2 stages are fetched from NAND or UART there is no problem. But when i use SD card for loading the 2 stages this problem crops up.

I even tried putting the Instruction Sync Barrier instruction before the jump to the code where the abort occurs... but no change.

Any pointers?

Thanks,
Vaibhav

P.S.: I could attach the code snippet for this if it helps
Parents
  • Arm Employee Badge
    Note: This was originally posted on 18th November 2010 at http://forums.arm.com



    277   mcr  p15, 0, r0, c7, c5, 0   @ invalidate icache



    This is only invalidating the i-cache to the point of unification (i.e. it is invalidating the L1 cache, but it isn't invalidating the L2 cache because that is a unified cache used for instructions and data). Are you enabling the L2? If you are that will need invalidating before you do so also - but you have to iterate over the number of sets and ways it has - there isn't an invalidate entire-L2 instruction.

    You also invalidate the cache before disabling it (if it was enabled at all). If it was enabled and you had any data in your d-cache which is not yet written back to main memory then you are going to lose it. You need to clean + invalidate the D cache, before you disable it.
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  • Arm Employee Badge
    Note: This was originally posted on 18th November 2010 at http://forums.arm.com



    277   mcr  p15, 0, r0, c7, c5, 0   @ invalidate icache



    This is only invalidating the i-cache to the point of unification (i.e. it is invalidating the L1 cache, but it isn't invalidating the L2 cache because that is a unified cache used for instructions and data). Are you enabling the L2? If you are that will need invalidating before you do so also - but you have to iterate over the number of sets and ways it has - there isn't an invalidate entire-L2 instruction.

    You also invalidate the cache before disabling it (if it was enabled at all). If it was enabled and you had any data in your d-cache which is not yet written back to main memory then you are going to lose it. You need to clean + invalidate the D cache, before you disable it.
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