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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3641 Questions
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  • Not Answered

    PendSV target secure state 0

    9924 views
    3 replies
    Latest over 4 years ago
    by Randall2
  • Suggested Answer

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    Latest over 4 years ago
    by sriram_s
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    IRQ Handler Branch 0

    3442 views
    4 replies
    Latest over 4 years ago
    by ronnyy
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    • DSP extensions
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    1 reply
    Latest over 4 years ago
    by 42Bastian Schick
  • Not Answered

    Cortex-A53 switching from EL2 to EL1 0

    • Cortex-A53
    • Baremetal
    16007 views
    22 replies
    Latest over 4 years ago
    by bluehat
  • Answered

    ldrex/strex breaked by third task ? 0

    2004 views
    1 reply
    Latest over 4 years ago
    by 42Bastian Schick
  • Answered

    Cortex-A55 PMU support 0

    • Cortex-A55
    5331 views
    4 replies
    Latest over 4 years ago
    by 42Bastian Schick
  • Answered

    Cortex-M3 DesignStart FPGA-Xilinx edition package bitstream incompatible on Arty A7-100T +1

    • FPGA Xilinx
    • Cortex-M3
    • DesignStart
    • Cortex-M
    7087 views
    6 replies
    Latest over 4 years ago
    by GVN
  • Not Answered

    Usage of NSCFG bit in S2CRn register in SMMUv2 0

    1764 views
    0 replies
    Started over 4 years ago
    by Mihir Joshi
  • Not Answered

    2515 CAN controller with rpi3 0

    6390 views
    6 replies
    Latest over 4 years ago
    by Joy784
  • Not Answered

    NEW ARM Programmer Code Question 0

    2363 views
    3 replies
    Latest over 4 years ago
    by David-WD8CXB
  • Not Answered

    Needs explanation of an assembly snippet 0

    6920 views
    4 replies
    Latest over 4 years ago
    by Joy784
  • Answered

    Issue with ARM926EJS uboot relocation to DDR +1

    • Arm9
    • arm926ej-s
    8426 views
    4 replies
    Latest over 4 years ago
    by Amarnath MB
  • Not Answered

    Help Programming ARM7TDMI-S in Assembly 0

    2256 views
    3 replies
    Latest over 4 years ago
    by 42Bastian Schick
  • Not Answered

    ARMv8-A Trap access of EL2 TTBR to EL3 0

    3714 views
    4 replies
    Latest over 4 years ago
    by Zenon (Zhilong) Xiu Arm Employee Badge
  • Not Answered

    L2C-310: clean&inval doesnt work properly 0

    • Cortex-A9
    • CoreLink L2C-310 Level 2 Cache Controller
    2474 views
    1 reply
    Latest over 4 years ago
    by Zenon (Zhilong) Xiu Arm Employee Badge
  • Not Answered

    Why only half of register bank is accessible in VFP's S0-31 view of register bank? 0

    • Armv7-A
    3217 views
    2 replies
    Latest over 4 years ago
    by Zenon (Zhilong) Xiu Arm Employee Badge
  • Suggested Answer

    acoustic application 0

    1740 views
    1 reply
    Latest over 4 years ago
    by sarun
  • Not Answered

    If I write the application on the M3, how hard it will be to compile it on M4 ? 0

    • Cortex-M3
    • Cortex-M4
    1958 views
    2 replies
    Latest over 4 years ago
    by MU234
  • Not Answered

    Memory Alignment for VSTM/VLDM Instructions on Cortex R52 0

    • Cortex-R52
    • Arm Assembly Language (ASM)
    2171 views
    1 reply
    Latest over 4 years ago
    by 42Bastian Schick
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