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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3581 Questions
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  • Not Answered

    MPU and TrustZone 0

    10002 views
    0 replies
    Started over 6 years ago
    by Talk2Joseph
  • Suggested Answer

    Cortex A15 SCU 0

    • Cortex-A15
    • Cortex-A
    12309 views
    1 reply
    Latest over 6 years ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    WT it non cache able memory when it broadcast at transaction 0

    • Cortex-A53
    • Cortex-A
    11105 views
    1 reply
    Latest over 6 years ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    reference source code to verify the Cortex-R52 0

    • Cortex-R52
    • Evaluation Boards
    4418 views
    1 reply
    Latest over 6 years ago
    by Jorney
  • Answered

    Where is the register definition of DHCSR for Cortex-M4 +1

    • Cortex-M4
    7225 views
    1 reply
    Latest over 6 years ago
    by Joseph Yiu Arm Employee Badge
  • Not Answered

    Related from zybo board 0

    9427 views
    0 replies
    Started over 6 years ago
    by Anuj kumar
  • Answered

    aarch64 Exception Level Sw itch from EL1 to EL0 0

    • EL1
    • EL3
    • AArch64
    • Raspberry Pi 3
    • EL0
    • QEMU
    • Cortex-A
    16828 views
    7 replies
    Latest over 6 years ago
    by michaelyuanfeng
  • Not Answered

    when I count the cycle of instructions in A53, I just want the cycle not including operation of memory and cache, which performance counts i should remove? thanks a lot! 0

    • Cortex-A53
    • Cache
    • Cortex-A
    • Memory
    9910 views
    0 replies
    Started over 6 years ago
    by sam0220
  • Answered

    MMU and Cache configuration 0

    • Cortex-A5
    • Cache
    • Memory Management Unit (MMU)
    • Cortex-A
    23853 views
    12 replies
    Latest over 6 years ago
    by Vanhealsing
  • Answered

    Significance of [MS] and [LS] in big-endian data bus in AHB5 Specification +1

    • AMBA
    • AHB5
    • AMBA 5
    • AHB
    13834 views
    1 reply
    Latest over 6 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    how to send data from open cv to arm 7 +1

    • Arm7
    • Computer Vision (CV)
    4248 views
    1 reply
    Latest over 6 years ago
    by Zhifei Yang
  • Answered

    Store data directly in RAM - ARM Cortex A53 +2

    12225 views
    2 replies
    Latest over 6 years ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    DBM bit in descriptor 0

    14842 views
    3 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    How can i get the real binary size of a Program 0

    3932 views
    2 replies
    Latest over 6 years ago
    by chrisKConti
  • Answered

    Running Bootloader out of RAM 0

    3375 views
    1 reply
    Latest over 6 years ago
    by chrisKConti
  • Answered

    How does Cortex-m4 core interact with other master devices? +1

    • Cortex-M
    • Cortex-M4
    3175 views
    1 reply
    Latest over 6 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    Loading Bootloader from Flash to RAM +1

    14713 views
    5 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Not Answered

    Statistical signal processing of radar signals 0

    1768 views
    0 replies
    Started over 6 years ago
    by shah87
  • Answered

    Capturing video on ARM Cortex M7 +1

    • Cortex-M7
    • Video Compression Standard
    6267 views
    6 replies
    Latest over 6 years ago
    by 42Bastian Schick
  • Answered

    Pipeline Stages in the Cortex-A53 +1

    19417 views
    2 replies
    Latest over 6 years ago
    by vstehle Arm Employee Badge
<>
Topics being discussed in this forum
  • AArch64
  • AMBA
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