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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3592 Questions
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  • Not Answered

    What will be the reason for MDR register not getting updated?? 0

    • Cortex-M
    • Arm Support
    1876 views
    0 replies
    Started over 5 years ago
    by omkardixi
  • Answered

    gicv3 aarch32 icc_hsre +1

    44741 views
    15 replies
    Latest over 5 years ago
    by PJ Nee
  • Not Answered

    Invalidate queue 0

    11372 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Answered

    Can I program M95640WP using CH341A Programmer +1

    2315 views
    1 reply
    Latest over 5 years ago
    by Oliver Beirne Arm Employee Badge
  • Not Answered

    AXI 4 Write Data Interleaving 0

    11958 views
    1 reply
    Latest over 5 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    Process ADC data, moved by DMA, using CMSIS DSP: what's the right way? 0

    • Cortex-M
    • CMSIS
    • Cortex-M4
    108568 views
    44 replies
    Latest over 5 years ago
    by KyleZ
  • Not Answered

    GCC 9 stack protector comparing address of stack guard not value 0

    3256 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    Booting of cortex M7 core, independently of cortex A53 core 0

    • Real Time Operating Systems (RTOS)
    • Cortex-A53
    • System on Chip (SoC)
    • Cortex-M7
    • operating systems
    2958 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    INSTRUCTION SET OF CORTEX M55? 0

    1540 views
    0 replies
    Started over 5 years ago
    by Sony
  • Not Answered

    STLink Utility Target Address 0

    1646 views
    0 replies
    Started over 5 years ago
    by JRMN
  • Answered

    Event Recorder with STM32F0 0

    • Cortex-M0
    • SRAM
    8445 views
    9 replies
    Latest over 5 years ago
    by Adam Lins
  • Answered

    Assembly code +1

    3599 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    How to test L1/L2 cache? 0

    15592 views
    2 replies
    Latest over 5 years ago
    by Zhiping Jiang
  • Not Answered

    Which bit fields are for Cortex-M4F SCB_ICSR.VECTORPENDING 0

    • Cortex-M4
    2903 views
    1 reply
    Latest over 5 years ago
    by 42Bastian Schick
  • Not Answered

    Tasks can't switch to others, always run at OSStartHang. but whitout boot code ,the app can run ok. the core of the chip is cortex-M0 +2

    8153 views
    7 replies
    Latest over 5 years ago
    by John_shi
  • Answered

    Speculative execution/loads on Cortex-A5 0

    • Cortex-A5
    • Pipeline Control and Execution
    • Cache
    16164 views
    5 replies
    Latest over 5 years ago
    by vstehle Arm Employee Badge
  • Answered

    Direct Virtual Interrupts (Timer Interrupt and IPI ) +1

    11380 views
    1 reply
    Latest over 5 years ago
    by vstehle Arm Employee Badge
  • Answered

    Inconsistent shareability domain on tlbi instructions 0

    • Cortex-A72
    • Cortex-A53
    14926 views
    3 replies
    Latest over 5 years ago
    by josecm
  • Not Answered

    Memory violation calling ATSAM3X8 0

    1584 views
    0 replies
    Started over 5 years ago
    by ccandido
  • Not Answered

    Instruction Count and Memory Access 0

    • CoreSight Debug and Trace
    • Musca-A
    • Cortex-M33
    4947 views
    2 replies
    Latest over 5 years ago
    by Lica
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