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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3593 Questions
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  • Answered

    When an exception is taken into account +1

    • Cortex-M7
    • Armv7 Exception Model
    • Armv7-M
    • Cortex-M3
    • Cortex-M
    • Cortex-M4
    4572 views
    3 replies
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    Number of Integer and Floating point execution units in M7 0

    • Cortex-M7
    • Cortex-M
    4115 views
    2 replies
    Latest over 7 years ago
    by Kallooran
  • Answered

    To run library functions on arm a53 core +1

    • Cortex-A53
    • AArch64
    • Cortex-A15
    • Cortex-A
    • AArch32
    9641 views
    3 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Suggested Answer

    When an exception is taken into account 0

    • Armv7 Exception Model
    • Armv7-M
    5468 views
    6 replies
    Latest over 7 years ago
    by Karolis
  • Answered

    Quad-Core Cortex A7 / MSDOS comparability +1

    • Cortex-A
    • Cortex-A7
    11278 views
    6 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Answered

    Invalid entry - mmu page tables +1

    • System MMU
    7804 views
    1 reply
    Latest over 7 years ago
    by MarekBykowski
  • Not Answered

    Cache ECC in Cortex-R5 & Event bus +1

    • Cortex-R
    • Cortex-R5
    • Cache
    5864 views
    2 replies
    Latest over 7 years ago
    by Johnson Berry
  • Not Answered

    How to run TF-M on keil M23/M33 fvp? 0

    • Address
    • RTX
    • Security
    • Armv8-A
    • TrustZone
    • Armv8-M
    • Interrupt
    8313 views
    0 replies
    Started over 7 years ago
    by matt-ma
  • Suggested Answer

    return from secure function to non-secure, why r4-r11 register not being cleared 0

    • TrustZone
    • Armv8-M
    11116 views
    4 replies
    Latest over 7 years ago
    by Wenchuan2018
  • Not Answered

    What is the fabric topology within the dynamiq cluster? 0

    • big.LITTLE
    • DynamIQ Shared Unit (DSU)
    5393 views
    0 replies
    Started over 7 years ago
    by kangzhang
  • Answered

    AM3352 core hang-up +1

    • Embedded Trace Buffer
    • Cortex-A
    • Cortex-A8
    • CoreSight
    15199 views
    9 replies
    Latest over 7 years ago
    by Kimura
  • Answered

    Text section size for executable created with ARMCC 6.7 is more than expected +1

    • AArch64
    • Cortex-A
    • Cortex-53
    7903 views
    1 reply
    Latest over 7 years ago
    by 42Bastian Schick
  • Not Answered

    Interrupts from the secure world to the non-secure world. 0

    • iOS
    • TrustZone
    • Armv8-M
    18496 views
    11 replies
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    A question about interrupt priority degrade 0

    • Architecture
    • web
    • CHI
    • Security
    • Class
    • TrustZone
    • Armv8-M
    • Internet of Things (IoT)
    9173 views
    2 replies
    Latest over 7 years ago
    by Wenchuan2018
  • Answered

    How to use FreeRTOS Scheduler with trustZone ARMV8-M M33 ? +1

    • ACE
    • Security
    • Cortex-M
    • TrustZone
    • Armv8-M
    10953 views
    2 replies
    Latest over 7 years ago
    by Simon
  • Answered

    Behaviour of HREADYOUTS of ahb_to_ahb_apb_async IP +1

    • AMBA
    6245 views
    1 reply
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    CortexM3 : Issue when image start address is other than 0x0 +1

    • Cortex-M3
    • Cortex-M
    • C
    3235 views
    1 reply
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    debug mode with Keil μVision 5 +1

    • Keil MDK
    • Armv8-M
    2702 views
    1 reply
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    CortexM3 +1

    • Cortex-M3
    • Cortex-M
    6581 views
    7 replies
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    code is not working for optimization setting O2 and O3 for Arch64bit Cortex-A53 process +1

    • Cortex-A53
    • AArch64
    • Armv8-A
    • Cortex-A
    7078 views
    1 reply
    Latest over 7 years ago
    by Zhifei Yang
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