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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3585 Questions
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  • Not Answered

    Trigger a Software Interrupt 0

    • Cortex-M
    • Cortex-M4
    • Interrupt
    6270 views
    1 reply
    Latest over 6 years ago
    by Haiyan Arm Employee Badge
  • Answered

    "BX LR" causing INVPC Usage Fault exception 0

    • Cortex-M7
    • Microcontroller (MCU)
    • Arm Assembly Language (ASM)
    • Cortex-M7 FVP
    8536 views
    2 replies
    Latest over 6 years ago
    by Sohaib
  • Not Answered

    What is the behavior for a "BKPT" instruction in a HardFault handler 0

    20887 views
    4 replies
    Latest over 6 years ago
    by Brett Bergquist
  • Answered

    Page Table Indexing using Virtual Address bits +1

    20706 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Suggested Answer

    translational table : block and table descriptor 0

    18945 views
    2 replies
    Latest over 6 years ago
    by Amitra29877
  • Answered

    Clarity on CMPMATCH event 0

    • Debug and Trace
    3637 views
    2 replies
    Latest over 6 years ago
    by jpthibault
  • Answered

    RK3399: how to configure Compute Library to use specific cores +1

    • Cortex-A53
    19778 views
    2 replies
    Latest over 6 years ago
    by vstehle Arm Employee Badge
  • Answered

    Memory barrier when accessing strongly ordered memory +1

    6915 views
    3 replies
    Latest over 6 years ago
    by Martin Weidmann Arm Employee Badge
  • Answered

    ARM assembly instruction for writing Zero to SPSR +1

    5114 views
    1 reply
    Latest over 6 years ago
    by 42Bastian Schick
  • Not Answered

    Inner/Outer share ability in Cortex R52 0

    2768 views
    0 replies
    Started over 6 years ago
    by Reco
  • Not Answered

    ARM board with SDI input 0

    17452 views
    0 replies
    Started over 6 years ago
    by Lawson
  • Not Answered

    Why A15 I-cache use PIPT while other series use VIPT 0

    16531 views
    0 replies
    Started over 6 years ago
    by haooo
  • Suggested Answer

    Cortex-A7 cache line size 0

    24932 views
    2 replies
    Latest over 6 years ago
    by haooo
  • Answered

    arm MMU-500 code samples 0

    21059 views
    7 replies
    Latest over 6 years ago
    by holder25
  • Answered

    For Armv8-M, is there a system register indicating the security state of the core? 0

    5150 views
    3 replies
    Latest over 6 years ago
    by Tao Lu
  • Not Answered

    Switching linker 0

    15465 views
    0 replies
    Started over 6 years ago
    by brianpl
  • Not Answered

    What options do I have for a GUI and an LCD? 0

    5850 views
    4 replies
    Latest over 6 years ago
    by AmyTheBUn
  • Answered

    OPS/core/cycle on A72 +1

    • Cortex-A72
    17523 views
    1 reply
    Latest over 6 years ago
    by vstehle Arm Employee Badge
  • Not Answered

    Cortex A9 Coresight TMC configuration 0

    15896 views
    0 replies
    Started over 6 years ago
    by Jan VdH
  • Not Answered

    RTOS for ARM A57(NVIDIA Jetson TX2 / TX2i) +1

    • Real Time Operating Systems (RTOS)
    • Cortex-A57
    • Linux
    20118 views
    2 replies
    Latest over 6 years ago
    by mea
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