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Hello,
On an exising project based on Cortex-R5, with a limited ATCM/BTCM resources, we need to start using Data/Instruction Cache with DDR (DRAM), to improve performance.
There is a lot scattered info in ARM documentation about caches - can you point me to some Refrence Code for:
1. Data/instruction Cache configuration during startup?
2. Data/instruction Cache configuration during run-time?
WRT Specific considerations using Data/Instruction Cache- can you point me to some documentation & Reference Code for:
3. Guidelines & Reference Code for CODE that one should keep in ATCM (typically holds interrupt or exception code that must be accessed at high speed,without any potential delay resulting from a cache miss), while using Data/Instruction Cache, and interactions with code/data in Instruction/Data Cache?
4. Guidelines & Reference Code for DATA that one should keep in BTCM (typically holds any block of data for intensive processing, such as audio or videoprocessing), while using Data/Instruction Cache, and interactions with data/code in Data/Instruction Cache?
5. Guidelines & Reference Code for CODE/DATA in Data/Instruction Cache, when RTOS is involved?
6. Guidelines & Reference Code for CODE/DATA in Data/Instruction Cache, when DMA is involved?
Thank-you