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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3582 Questions
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  • Answered

    DWT's watchpoint exception can not be issued when interrupt is disabled 0

    2015 views
    2 replies
    Latest over 4 years ago
    by sword_i@sina.com
  • Not Answered

    Does TLB save level-1 page directory entries? +1

    • Arm11
    5418 views
    3 replies
    Latest over 4 years ago
    by Qualls
  • Not Answered

    Please fill in: 2021 ML on MCUs and DSPs (tinyML) Developer Survey 0

    • Machine Learning (ML)
    • Cortex-M
    1249 views
    0 replies
    Started over 4 years ago
    by Wen Chou Arm Employee Badge
  • Not Answered

    Unsupported exclusive Data Abort 0

    1561 views
    0 replies
    Started over 4 years ago
    by XNoOp
  • Not Answered

    Faultmask, Caches and startup code (a writeup). 0

    1109 views
    0 replies
    Started over 4 years ago
    by 42Bastian Schick
  • Not Answered

    Hard fault error after adding static library into STM32F205VET6 0

    • STM32 F2
    • Cortex-M3
    • 3 (HardFault)
    1823 views
    2 replies
    Latest over 4 years ago
    by AshishD
  • Suggested Answer

    Cotex M4 ---MPU. After I override a privilleged region, it seems the write permission can't be upgraded?what is wrong? 0

    1622 views
    2 replies
    Latest over 4 years ago
    by Lindaqiuqiu
  • Not Answered

    can the Cortex-R5 processor support Cross Trigger Interface (CTI)? 0

    1312 views
    0 replies
    Started over 4 years ago
    by chenyu
  • Not Answered

    Host compilations of code which include the CMSIS headers 0

    • GCC
    • CMSIS
    • Cortex-M4
    • Test and Validation
    2082 views
    2 replies
    Latest over 4 years ago
    by JWMISEU
  • Not Answered

    Is pre-compiled ARM9 libs able to run on an ARM11 chip 0

    • Arm9
    • Arm11
    6571 views
    6 replies
    Latest over 4 years ago
    by Aimeee
  • Not Answered

    Why I am getting hardfault when static library is added into the project? 0

    • STM32 F2
    1518 views
    1 reply
    Latest over 4 years ago
    by 42Bastian Schick
  • Not Answered

    How to stop coresight sink on CPU exception 0

    6028 views
    6 replies
    Latest over 4 years ago
    by Aimeee
  • Answered

    Inner/Outer Cacheability in Cortex V8-R +1

    8597 views
    4 replies
    Latest over 4 years ago
    by XNoOp
  • Not Answered

    how to connect the ACP (accelerate coherence port) interface with my SoC system 0

    1839 views
    0 replies
    Started over 4 years ago
    by chenyu
  • Not Answered

    What happens if NMI is triggered while processing an existing NMI? 0

    • 2 (NMI)
    • Interrupt Handling
    • Cortex-M7
    2511 views
    2 replies
    Latest over 4 years ago
    by Robert McNamara
  • Answered

    How is AHB faster than APB? The transfer will be a normal single transfer. 0

    19828 views
    5 replies
    Latest over 4 years ago
    by Manjuja
  • Not Answered

    Loadind PDSC Debug Destryption failed for STM32L010 0

    2539 views
    5 replies
    Latest over 4 years ago
    by slawek krzysiek
  • Not Answered

    [M0+] Get CONTROL register on HardFault Handler 0

    • 3 (HardFault)
    • Cortex-M0+
    1597 views
    0 replies
    Started over 4 years ago
    by riglesias
  • Not Answered

    Can multiple cores perform L2 cache maintenance operations to flush (say) different addresses from the L2 cache. 0

    2760 views
    0 replies
    Started over 4 years ago
    by conradomaher
  • Answered

    _Min_Heap_Size and _Min_Stack_Size 0

    2665 views
    2 replies
    Latest over 4 years ago
    by Gknr
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