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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3585 Questions
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  • Answered

    Can we reset L2 subsystem for cortex-A57? +1

    • Cortex-A57
    • Cortex-A
    7850 views
    1 reply
    Latest over 6 years ago
    by MarekBykowski
  • Answered

    what is non-secure callable and when can use it ? 0

    • TrustZone
    • Armv8-M
    11657 views
    3 replies
    Latest over 6 years ago
    by Simon
  • Answered

    Why thumb code can only access r0-r7? 0

    • Armv6-M
    • T32 (Thumb)
    • Arm Thumb Procedure Call Standard (ATPCS)
    • Cortex-M
    5213 views
    4 replies
    Latest over 6 years ago
    by Wenchuan2018
  • Answered

    Behavior for other data on a STR (ARMv7-A) +1

    • Armv7-A
    • Cortex-A
    8086 views
    2 replies
    Latest over 6 years ago
    by superdesk
  • Suggested Answer

    ARM PMU access DRAM Event 0

    • Dynamic Random Access Memory (DRAM)
    • Cortex-A
    • Cortex-A7
    11619 views
    5 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Answered

    LDREX/STREX on the M3,M4,M7 0

    • Cortex-M7
    • Cortex-M3
    • Cortex-M
    • Cortex-M4
    17112 views
    9 replies
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    Confusion about exception level of ARMv8 +1

    • Cortex-A57
    • AArch64
    • Armv8-A
    • Cortex-A
    • AArch32
    29210 views
    6 replies
    Latest over 7 years ago
    by Chau Huynh
  • Not Answered

    How do I probe in for Power measurement in A9 using PAPI tool 0

    • Cortex-A9
    • Cortex-A
    • Linux
    7110 views
    0 replies
    Started over 7 years ago
    by Bharadwaj Gorthy
  • Not Answered

    ARM MUL instruction 0

    • Cortex-A
    • Cortex-A7
    26068 views
    13 replies
    Latest over 7 years ago
    by Sean Dunlevy
  • Answered

    Ways to Tx data from Cortex R5 to A53? 0

    • Cortex-A53
    • Cortex-A
    15607 views
    8 replies
    Latest over 7 years ago
    by Zombie_Ashish
  • Suggested Answer

    MIPS of Arm cortex m7 +1

    • Cortex-M7
    • Cortex-M
    11556 views
    5 replies
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    Which Arm processor to select? +1

    • Cortex-M
    3049 views
    1 reply
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    When an exception is taken into account +1

    • Cortex-M7
    • Armv7 Exception Model
    • Armv7-M
    • Cortex-M3
    • Cortex-M
    • Cortex-M4
    4545 views
    3 replies
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    Number of Integer and Floating point execution units in M7 0

    • Cortex-M7
    • Cortex-M
    4100 views
    2 replies
    Latest over 7 years ago
    by Kallooran
  • Answered

    To run library functions on arm a53 core +1

    • Cortex-A53
    • AArch64
    • Cortex-A15
    • Cortex-A
    • AArch32
    9612 views
    3 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Suggested Answer

    When an exception is taken into account 0

    • Armv7 Exception Model
    • Armv7-M
    5426 views
    6 replies
    Latest over 7 years ago
    by Karolis
  • Answered

    Quad-Core Cortex A7 / MSDOS comparability +1

    • Cortex-A
    • Cortex-A7
    11206 views
    6 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Answered

    Invalid entry - mmu page tables +1

    • System MMU
    7737 views
    1 reply
    Latest over 7 years ago
    by MarekBykowski
  • Not Answered

    Cache ECC in Cortex-R5 & Event bus +1

    • Cortex-R
    • Cortex-R5
    • Cache
    5824 views
    2 replies
    Latest over 7 years ago
    by Johnson Berry
  • Not Answered

    How to run TF-M on keil M23/M33 fvp? 0

    • Address
    • RTX
    • Security
    • Armv8-A
    • TrustZone
    • Armv8-M
    • Interrupt
    8307 views
    0 replies
    Started over 7 years ago
    by matt-ma
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Topics being discussed in this forum
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  • Arm Assembly Language (ASM)
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