Arm Community
Arm Community
  • Site
  • User
  • Site
  • Search
  • User
Support forums
Support forums
Architectures and Processors forum
  • Jump...
  • Cancel
  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3627 Questions
Help a member

Have a question? If you can, please take a moment to also see if there is a question that you are able to answer.

  • Tags
  • RSS
  • More actions
  • Cancel
Other forums
  • AI forum

  • Architectures and Processors forum

  • Arm Development Platforms forum

  • Arm Development Studio forum

  • Arm Virtual Hardware forum

  • Automotive forum

  • Compilers and Libraries forum

  • Embedded and Microcontrollers forum

  • High Performance Computing (HPC) forum

  • Internet of Things (IoT) forum

  • Keil forum

  • Laptops and Desktops forum

  • Mobile, Graphics, and Gaming forum

  • Morello forum

  • Operating Systems forum

  • Servers and Cloud Computing forum

  • SoC Design and Simulation forum

  • SystemReady Forum

  • TOSA forum

  • Answered

    Help with porting Intel AVX to arm64 +1

    • AArch64
    • Arm64
    16867 views
    1 reply
    Latest over 7 years ago
    by jtzhou
  • Answered

    MMU - Permission Fault with EL1 access +1

    • Cortex-A53
    • AArch64
    • Raspberry Pi 3
    • Armv8-A
    • Memory Management Unit (MMU)
    16808 views
    3 replies
    Latest over 7 years ago
    by Dumitru
  • Answered

    Why is PC-relative addressing deprecated for STR and VSTR in ARMv7-M4? +1

    16885 views
    8 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Answered

    Neoverse N1 CPU Questions +1

    13146 views
    4 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Answered

    Issues in Cortex A9 bareboard code if L2 cache controller registers are not mapped +1

    • Cortex-A9
    • CoreLink L2C-310 Level 2 Cache Controller
    • Memory Management Unit (MMU)
    • Cortex-A
    13400 views
    8 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Answered

    M0+ Stack Pointer (PSP/MSP) Clarification 0

    • Cortex-M0
    • Cortex-M3
    • Thumb
    • Cortex-M
    • Arm Assembly Language (ASM)
    • C
    18099 views
    15 replies
    Latest over 7 years ago
    by Sean Dunlevy
  • Answered

    ARMv8-A: Virtual to physical translation sometime "fails" 0

    • Armv8-A
    8502 views
    1 reply
    Latest over 7 years ago
    by 42Bastian Schick
  • Answered

    ARM cortex R5 Performance is decreased by 20% after enabling Cache coherence 0

    • Cortex-A53
    • Cortex-R
    • CoreLink CCI-400 Cache Coherent Interconnect
    • Cache coherency
    • Cortex-R5
    • Cortex-A
    10963 views
    6 replies
    Latest over 7 years ago
    by Sandeep Bobba
  • Answered

    How to flush the pipeline of a processor using XScale-compatible Assembly? +1

    • Arm Development Studio
    • Cortex-A15
    • Cortex-A
    • Arm Assembly Language (ASM)
    10308 views
    3 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Answered

    Non-secure EXC_RETURN value to Secure HardFault Handler 0

    10745 views
    2 replies
    Latest over 7 years ago
    by Rajiv
  • Answered

    JTAG to TrustZone Cortex-M33 0

    • CHI
    • TrustZone
    • Armv8-M
    12043 views
    2 replies
    Latest over 7 years ago
    by Ronan Synnott Arm Employee Badge
  • Answered

    ARM64: LDR (register) SXTX extend +1

    • AArch64
    • Arm64
    15650 views
    5 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Answered

    Cortex-A5 and configuration for real time task +1

    • APB
    • Cortex-A5
    • Memory Management Unit (MMU)
    • Cortex-A
    • AHB
    11852 views
    4 replies
    Latest over 7 years ago
    by Vanhealsing
  • Not Answered

    DMIPS calculation for application software on ARM Cortex A7 0

    • Software
    • Application Software
    • Cortex-A7
    12852 views
    0 replies
    Started over 7 years ago
    by Sanjeev Kumar
  • Answered

    Cortex-M0+ privileged/unprivileged extensions 0

    • Cortex-M0
    • Armv6-M
    • Cortex-M
    6089 views
    2 replies
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    Development platforms, compilers for TrustZone 0

    • Architecture
    • Address
    • CHI
    • Security
    • TrustZone
    • Armv8-M
    10379 views
    1 reply
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    Cortex-M register RAM and Flash periodical check? +1

    • Cortex-M
    • Cortex-M4
    3431 views
    1 reply
    Latest over 7 years ago
    by Appala Naidu
  • Answered

    A53 - MMU vs MPU +1

    • Cortex-A53
    • System MMU
    13164 views
    4 replies
    Latest over 7 years ago
    by Umang Mehta
  • Answered

    Non-secure peripheral with a secure interrupt handler 0

    • Layout
    • Address
    • TrustZone
    • Armv8-M
    • Memory
    13690 views
    5 replies
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Answered

    Whether Armv7-A has a Write Buffer 0

    • Armv7-A
    • Cortex-A
    12930 views
    8 replies
    Latest over 7 years ago
    by Youq
<>