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  • Description The latest forum discussions for Arm architectures and Cortex-A, R, M, and classic processors.
  • Threads 3627 Questions
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  • Not Answered

    How to pass arguments to a bare-metal app using u-boot 0

    • U-Boot
    11519 views
    0 replies
    Started over 7 years ago
    by josecm
  • Not Answered

    Is it OK to bypass all clock gates in Cortex-R52? 0

    • Cortex-R52
    • Clocking Structures & Timing Mechanisms
    • SoC FPGA
    2715 views
    0 replies
    Started over 7 years ago
    by Zack Yang
  • Not Answered

    OT but Atmel are no help 0

    2505 views
    0 replies
    Started over 7 years ago
    by Sean Dunlevy
  • Answered

    Understanding XDMAC on Cortex-M7 +1

    • Cortex-M7
    • Cortex-M
    5126 views
    1 reply
    Latest over 7 years ago
    by Vanhealsing
  • Answered

    Looking for an eval board with octa core Armv8 CPU 0

    • AArch64
    18553 views
    11 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Not Answered

    Fixed-point calculation using CMSIS_library 0

    • Cortex-M0
    • Digital Signal Processor (DSP)
    • CMSIS
    • Cortex-M4
    7726 views
    0 replies
    Started over 7 years ago
    by MnP_Junho
  • Not Answered

    MPU and TrustZone 0

    10098 views
    0 replies
    Started over 7 years ago
    by Talk2Joseph
  • Suggested Answer

    Cortex A15 SCU 0

    • Cortex-A15
    • Cortex-A
    12461 views
    1 reply
    Latest over 7 years ago
    by Christopher Tory Arm Employee Badge
  • Suggested Answer

    WT it non cache able memory when it broadcast at transaction 0

    • Cortex-A53
    • Cortex-A
    11247 views
    1 reply
    Latest over 7 years ago
    by Christopher Tory Arm Employee Badge
  • Not Answered

    reference source code to verify the Cortex-R52 0

    • Cortex-R52
    • Evaluation Boards
    4530 views
    1 reply
    Latest over 7 years ago
    by Jorney
  • Answered

    Where is the register definition of DHCSR for Cortex-M4 +1

    • Cortex-M4
    7571 views
    1 reply
    Latest over 7 years ago
    by Joseph Yiu Arm Employee Badge
  • Not Answered

    Related from zybo board 0

    9474 views
    0 replies
    Started over 7 years ago
    by Anuj kumar
  • Answered

    aarch64 Exception Level Sw itch from EL1 to EL0 0

    • EL1
    • EL3
    • AArch64
    • Raspberry Pi 3
    • EL0
    • QEMU
    • Cortex-A
    17348 views
    7 replies
    Latest over 7 years ago
    by michaelyuanfeng
  • Not Answered

    when I count the cycle of instructions in A53, I just want the cycle not including operation of memory and cache, which performance counts i should remove? thanks a lot! 0

    • Cortex-A53
    • Cache
    • Cortex-A
    • Memory
    9977 views
    0 replies
    Started over 7 years ago
    by sam0220
  • Answered

    MMU and Cache configuration 0

    • Cortex-A5
    • Cache
    • Memory Management Unit (MMU)
    • Cortex-A
    24641 views
    12 replies
    Latest over 7 years ago
    by Vanhealsing
  • Answered

    Significance of [MS] and [LS] in big-endian data bus in AHB5 Specification +1

    • AMBA
    • AHB5
    • AMBA 5
    • AHB
    14194 views
    1 reply
    Latest over 7 years ago
    by Colin Campbell Arm Employee Badge
  • Answered

    how to send data from open cv to arm 7 +1

    • Arm7
    • Computer Vision (CV)
    4343 views
    1 reply
    Latest over 7 years ago
    by Zhifei Yang
  • Answered

    Store data directly in RAM - ARM Cortex A53 +2

    12684 views
    2 replies
    Latest over 7 years ago
    by Martin Weidmann Arm Employee Badge
  • Suggested Answer

    DBM bit in descriptor 0

    15387 views
    3 replies
    Latest over 7 years ago
    by 42Bastian Schick
  • Answered

    How can i get the real binary size of a Program 0

    4195 views
    2 replies
    Latest over 7 years ago
    by chrisKConti
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